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RISC-V Developer Boards to drive innovation

We are at an incredible inflection point for RISC-V. We are making history and we want you to be a part of it! RISC-V is…

New Methodologies Create New Opportunities | Brian Bailey, Semiconductor Engineering

Does RISC-V processor verification provide common ground to develop a new verification methodology, and will that naturally lead to new and potentially open tools? Experts…

Video: PULSE Sensor Demo using VEGA Processor [ RISC-V ISA] | VEGA Processors

Demonstrating PULSE Sensor using VEGA Microprocessor based on RISC-V ISA

Video: New Online Courses For RISC-V | Linux Foundation

RISC-V is a free and open instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. To help individuals get…

Pineapple ONE 32 bit RISC-V homemade CPU | filip.szkandera

In this article I will describe how I designed and made a functional 32 bit RISC-V CPU at home. Specifications: "Max" clock speed: 500 kHz…

Renode 1.12 release – new platforms, sensors and debugging features | Antmicro

Originally created to meet Antmicro’s internal need for a flexible system design and testing tool, Renode has been in use by numerous projects and organizations including internet…

Memory Availability Comparison between ESP32 and ESP32-C3 | Amey Inamdar: The ESP Journal

Espressif launched ESP32-C3 at the end of 2020. It’s very well received and now it’s already in the mass production state. ESP32-C3 provides Wi-Fi and…

Video: 16X4 LCD Display Demo using VEGA Processor [ RISC-V ISA] | VEGA Processors

Demonstrating 16X4 LCD Display using VEGA Microprocessor based on RISC-V ISA

AI-Thinker introduces 5 ESP32-C3 modules pin compatible with ESP8266 & ESP32 modules | Jean-Luc Aufranc, CNX Soft

ESP32-C3 is the first RISC-V wireless SoC from Espressif Systems, and at the time of the initial announcement promised to cost about the same as…

Video: RISC V Chip Testing Demo | Nanoelectronics and Computing Research Laboratory

Functional Test of Fabricated RISC-V Processor Cores to Demonstrate Hardware Security

New Online Courses For RISC-V | The Linux Foundation

RISC-V is a free and open instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. To help individuals get…

Andes Announces the New Upgrade of AndeSight™ IDE v5.0: a comprehensive software solution to accelerate RISC-V AI and IoT developments | Globe Newswire

HSINCHU CITY, TAIWAN, April 23, 2021 (GLOBE NEWSWIRE) -- Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores…

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SiFive shows there is life in RISC-V | Nick Farrell, Fudzilla

Will 2020 be the year of RISC-V? SiFive has unveiled a new computer featuring the company's SiFive FU740 processor based on RISC-V architecture. According to…

May RISC-V Processors compete with Intel, Arm, and AMD?

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Engage in Unmatched RISC-V Business with SiFive | Jeremy Hellstrom, PC Perspective

It's not Sci-Fi, it's the new HIFIVE unmatched RISC-V Computer Two years ago HiFive released their Unleashed RISC-V, a fully functional PC based on the…

SiFive’s RISC-V PC coming soon for $665 | Brad Linder, Liliputing

promised, SiFive has unveiled a new computer featuring the company’s SiFive FU740 processor based on RISC-V architecture. The company, which has been making RISC-V chips…

HiFive Unmatched ushers in a new era of RISC-V Linux development with a platform in a PC form factor (video) | Bits inside by René Rebe

Finally a high(er) performance #RISCV #Linux development with a platform in a PC #miniitx form factor?]]>

The Heart of RISC-V Development is Unmatched | James Prior, SiFive

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