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Video: Automatic end-to-end formal verification of RISC-V processors | Axiomise Formal Verification Channel

Processor verification has always been a significant challenge. With the open-source RISC-V® ISA, we see an emerging revolution for processor design with lots of new…

Why, and how, we’ll all be making our own computer chips in the future… | Rob Taylor

If you read the tech news, it can’t have slipped your attention that significant changes are a foot in the computer chip industry. New chief…

Is RISC-V China’s Semiconductor Salvation? | Tobias Mann

U.S. trade restrictions and growing pressure from the Chinese Communist Party to end reliance on foreign chipmakers has left many Chinese technology companies understandably worried. Over the…

Enabling RISC-V Based System Development | Sandeep Nasa and Sagar Thakran, Logic Fruit Technologies

Verifying a RISC-V Core-Based Design: A Primer This article focuses on providing a jump start on RISC-V development. It shows how to build a verification…

SiFive and ArchiTek Enable Secure, Private, Flexible Edge AI Computing With AiOnIc® Processor | SiFive

New Edge AI processor accelerates key workloads while offering flexibility for changing AI needs SAN MATEO, Calif. – March 18, 2021 – SiFive, Inc., the…

K210 AI Accelerator a Compact Raspberry Pi HAT for Computer Vision Applications | Saumitra Jagdale

XaLogics’s AI Accelerator with K210 SoC comes with a dual-core RISC-V AI processor featuring low power consumption than its competing Coral USB Accelerator, and Intel…

RISC-V Security Forum 2021 – Schedule Announced!

The RISC-V Forums, hosted by RISC-V International, are short-form, single-topic, deep-dive virtual events. This is the spirit of RISC-V events - providing technical content to…

Using TL-Verilog for FPGAs | Shivani Shah

A few months back, I came across a workshop titled ‘RISC-V based Microprocessor for You in Thirty Hours (MYTH)’, that was about designing RISC-V core…

3 RISC-V Forums Scheduled | insideHPC

The RISC-V Forum will hold three conferences starting next month that are free of charge to members and non-members and designed to provide deep-dive technical content…

Imperas’ RV32/64K Crypto Architectural Validation Test Suites Now Included in RISC-V Verification Ecosystem | Chad Cox Embedded Computing Design

Imperas Software released its latest update to the RISC-V architectural validation test suites for the RV32/64K Crypto (scalar) extension. The released tests support the RISC-V ISA…

DARPA pitted 500+ hackers against this computer chip. The chip won. | Gabe Cherry Michigan Engineering

University of Michigan’s MORPHEUS technology emerges unscathed from bug bounty effort.| Medium Read An “unhackable” computer chip lived up to its name in its first bug…

Ron Black Joins Codasip as Executive Chairman

Munich, Germany – March 16th, 2021 – Codasip, the leading supplier of customizable RISC‑V processor IP, announced that semiconductor industry veteran Dr Ron Black has joined…

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Bluespec, Inc. Releases RISC-V Explorer: A Fast, Free, Accurate Way to Evaluate RISC-V

“Companies around the world are acting on the new freedom to innovate with RISC-V, but many are overwhelmed by the sheer number of RISC-V offerings…