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An Insider’s View Of Verifying Custom RISC-V Processor Cores | Shubhodeep Roy Chodhury, Semiconductor Engineering
Enabling Edge AI Vision with RISC-V and a Silicon Platform | Tom Simon
MIPS, China’s Loongson CPU Are Both Going All-in on RISC-V | Joel Hruska
Video: PineTalk episode 4: GPU-o-Rama | Pine64
Home News Hackers hack at unhackable new chip for three months. Chip remains unhacked | Dave James, PC GamerXen and the RISC-V Hypervisor Extension
Growing an Open and Inclusive Community
如何利用RISC-V SoC同时处理5G与AI工作负载？| How to use RISC-V SoC to handle 5G and AI workloads at the same time? | Sally Ward-Foxton (Chinese)OpenHW Group and Mitacs announce OpenHW Accelerate | OpenHW Group
Bluetrum AB32VG1 board features AB5301A Bluetooth RISC-V MCU, runs RT-Thread RTOS | Jean-Luc Aufran, CNX SoftwareCODASIP ANNOUNCES COMMERCIAL ADD-ONS TO SWERV CORE® EH1 | Codasip
Alibaba On The Bleeding Edge Of RISC-V With XT910 | Jeffrey Burt, The Next Platform
Hot Chips 2020 Live Blog: Alibaba Xuantie-910 RISC-V CPU | Dr. Ian Cutress, Anandtech
An Insider’s View Of Verifying Custom RISC-V Processor Cores | Shubhodeep Roy Chodhury, Semiconductor EngineeringThis article is derived from a talk at the RISC-V Summit in December 2020 that Bill McSpadden, principal verification engineer at Seagate Technology, gave on the…
Enabling Edge AI Vision with RISC-V and a Silicon Platform | Tom SimonAI vision processing moving to the edge is an undeniable industry trend. OpenFive, the custom silicon business unit of SiFive, discusses this trend with compelling…
MIPS, China’s Loongson CPU Are Both Going All-in on RISC-V | Joel HruskaRISC-V is having itself a moment. What began as an effort to produce an open-source ISA for low-end microcontrollers and other simple kinds of chips…
Video: PineTalk episode 4: GPU-o-Rama | Pine64In the fourth episode of PineTalk, Ezra and Peter discuss Matrix video calling on the PinePhone, open source GPUs on RISC-V and go though your…
Home News Hackers hack at unhackable new chip for three months. Chip remains unhacked | Dave James, PC GamerUniversity of Michigan's Morpheus chip has passed its stiffest security test to far. The dangerous-titled 'unhackable' processor has survived its biggest hacking test remarkably unscathed.…
Xen and the RISC-V Hypervisor ExtensionAs some readers may know, we've been working on porting Xen to RISC-V. This blog looks at why we care about RISC-V and how RISC-V…
Growing an Open and Inclusive CommunityCollaboration underpins everything we do in the RISC-V community. That’s why we encourage everyone to join us and participate, and why we are working hard…
如何利用RISC-V SoC同时处理5G与AI工作负载？| How to use RISC-V SoC to handle 5G and AI workloads at the same time? | Sally Ward-Foxton (Chinese)硅谷初创公司EdgeQ最近吸引了业界关注，该公司计划开发RISC-V SoC，来探索5G和AI处理工作负载之间的数学相似性。他们的首要目标市场将是电信基础设施，AI将被用于5G网络，比如检测可能会出现恶意攻击的异常行为。随后将进军客户端应用市场，比如工业机器人、汽车和无人机，其主要应用是AI加速，同时SoC还支持5G网络连接。 Read the full article
OpenHW Group and Mitacs announce OpenHW Accelerate | OpenHW GroupToday, OpenHW Group and Mitacs announced OpenHW Accelerate, a $22.5M multi-year co-funded research program, the world’s first open-source hardware research program of its kind. OpenHW…
Bluetrum AB32VG1 board features AB5301A Bluetooth RISC-V MCU, runs RT-Thread RTOS | Jean-Luc Aufran, CNX SoftwareBluetrum, a Shenzhen-based fabless company focusing on audio chips, has designed the AB32VG1 board based on its AB5301A Bluetooth RISC-V MCU for general-purpose and audio applications.…
CODASIP ANNOUNCES COMMERCIAL ADD-ONS TO SWERV CORE® EH1 | CodasipMunich, Germany – March 9th, 2021 – Codasip, the leading supplier of customizable RISC‑V processor IP, announced three commercially licensed add-ons to the Western Digital SweRV…
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Alibaba On The Bleeding Edge Of RISC-V With XT910 | Jeffrey Burt, The Next PlatformRead the full article]]>
Hot Chips 2020 Live Blog: Alibaba Xuantie-910 RISC-V CPU | Dr. Ian Cutress, AnandtechRead the full live-blog.]]>