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EU Seeks to Double Share of World Chip Market by 2030 in ‘Digital Sovereignty’ Drive | Daniel Michaels and Stu Woo, WSJ

BRUSSELS—The European Union is pledging more than $150 billion to develop next-generation digital industries this decade as it seeks to reverse a widening gap with…

Codasip Announces Commercial Add-Ons to SweRV Core EH1

Munich, Germany – March 9th, 2021 – Codasip, the leading supplier of customizable RISC‑V processor IP, announced three commercially licensed add-ons to the Western Digital SweRV…

Wait, What? MIPS Becomes RISC-V Classic CPU Company Exits Bankruptcy, Throws in the Towel |Jim Turley, Electronics Engineering Journal

What a long, strange trip it’s been. MIPS Technologies no longer designs MIPS processors. Instead, it’s joined the RISC-V camp, abandoning its eponymous architecture for…

Open Source Processors for Next-Generation Storage Controllers | Eye on Tech

Open source software tools are enabling a high level of innovation for storage controllers and data center architectures. Here is an introduction to storage controller…

Enter at Your Own RISC! – Intermezzo mit RISC-V und dem ESP32-C3 | Intermezzo with RISC-V and the ESP32-C3 | Michael Stal, heise (German)

In den letzten Folgen war vom Raspberry Pi Pico die Rede. Bevor sich das Blog weiterhin dem Pico widmet, adressiert dieses Extra-Posting den neuen Microcontroller…

RISC-V Execution Stages | Maven Silicon

This video explains the execution stages of a RISC-V processor and how it executes all the instructions. Follow this RISC-V video blog series to obtain…

IAR Systems announces availability of RISC-V development tools with certification for IEC 61508 and ISO 26262 | PR Newswire

UPPSALA, Sweden, March 4, 2021 /PRNewswire/ -- IAR Systems®, the future-proof supplier of software tools and services for embedded development, announces the availability of a certified edition of…

GitHub Actions self-hosted runners, Build Event Server and Google Cloud | Antmicro

Continuous Integration and smart lifecycle management are key for high-tech product development, which is often a complex and multi-faceted process that requires automation to be…

Free Courses Now Available to Learn ‘RISC-V’ by The Linux Foundation & RISC-V International | Sourav Rudra, It’s Foss News

The Linux Foundation is the official organization behind Linux and is at the forefront for collaboration on open-source software, open hardware, open data and open standards.…

RISC-V Fast Tracks Simpler Extensions | eeJournal, Jim Turley

One of the charming aspects of RISC-V is that it’s so… flexible. As an open-source processor specification, absolutely anyone can use it, modify it, and…

Linux Foundation and RISC-V International launch free RISC-V training classes | Steven J. Vaughan-Nichols, ZDNet

RISC-V, the emerging open-source instruction set processor architecture, is growing up. Sure, most of the attention has come from hardware hackers playing on RISC-V processors…

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Verification and Validation in the cybersecure automotive world

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Are we facing a future of virtual events?

Are we facing a future of virtual events? appeared first on UltraSoC.]]>