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Linux 5.10 LTS release – Main changes, Arm, MIPS and RISC-V architectures | Jean-Luc Aufranc, CNX Software
RISC-V Microarchitecture for Kids??!! | Steve Hoover, Redwood EDA
RISC-V International Annual Awards
ET-SoC-1 Chip with More Than 1,000 RISC-V Cores Aimed at Accelerating Machine Learning | Abhishek Jadhav, hackster.io
Compiling a Benchmark for RISC-V | TechTechPotato
RISC-V Summit 2020 showcases a growing ecosystem and a wider application spectrum | Roberto Frazzoli, EDACafe'
Embedded Studio for RISC-V now comes with SEGGER Linker | Neil Tyler, New Electronics
The Genius of RISC-V Microprocessors | Erik Engheim, Medium
Calista Redmond of RISC-V International Tells Us About Its Open-Source Development Model and COVID-19 | Kossi Adzo, startup.info
Linker Shrinks RISC-V Application Size | Nick Flaherty, eeNews Europe
Seagate Announces Its Own RISC-V Cores for Future Storage Controllers | Joel Hruska, Extreme Tech
Linux 5.10 LTS release – Main changes, Arm, MIPS and RISC-V architectures | Jean-Luc Aufranc, CNX Softwarehas just released Linux 5.10: Ok, here it is – 5.10 is tagged and pushed out. I pretty much always wish that the last week was…
RISC-V Microarchitecture for Kids??!! | Steve Hoover, Redwood EDALast month I had the great pleasure of sharing a blog post about Nicholas Sharkey, an amazing 13 year-old who participated with graduate students and…
RISC-V International Annual AwardsRISC-V Innovation Founders Awards In recognition of the industry impact initiated by the technical leadership and generous contribution of the founding inventors and innovators of…
ET-SoC-1 Chip with More Than 1,000 RISC-V Cores Aimed at Accelerating Machine Learning | Abhishek Jadhav, hackster.ioAt the RISC-V Summit 2020, Art Swift, CEO of Esperanto Technologies, announced the development of a chip based on the open source RISC-V architecture with…
Compiling a Benchmark for RISC-V | TechTechPotatoWe've been after a compile benchmark for a while, something that was easy enough to run on multiple systems but also portable, could be automated,…
RISC-V Summit 2020 showcases a growing ecosystem and a wider application spectrum | Roberto Frazzoli, EDACafe'here and here – commissioned by Mentor. In fact, 2020 has been a year of growth for this open instruction set architecture, as underlined by Calista Redmond, CEO…
Embedded Studio for RISC-V now comes with SEGGER Linker | Neil Tyler, New ElectronicsSEGGER’s Embedded Studio for RISC-V now comes with the SEGGER Linker in addition to the GNU linker. The SEGGER Linker has been developed from…
The Genius of RISC-V Microprocessors | Erik Engheim, MediumSince the RISC and CISC wars that raged in the late 1990s, people have claimed that RISC and CISC doesn’t matter anymore. Many will claim…
Calista Redmond of RISC-V International Tells Us About Its Open-Source Development Model and COVID-19 | Kossi Adzo, startup.infoFirst of all, how are you and your family doing in these COVID-19 times? Calista Redmond: We’re doing well, thank you. We’re fortunate to be keeping…
Linker Shrinks RISC-V Application Size | Nick Flaherty, eeNews EuropeSegger is a custom Linker in addition to the GNU linker. This is based on the same code as the Segger Linker for ARM, adding integrated integrity check…
Seagate Announces Its Own RISC-V Cores for Future Storage Controllers | Joel Hruska, Extreme Techchips, which are not referred to by any codename or brand, come in two flavors: A high-performance core and an area-optimized core. The high performance core…
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