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Architectures for Matrix Extension in CPU | Jiang Zhao, Alibaba Cloud
Porting GNOME OS to Microchip’s PolarFire® SoC FPGA Icicle Kit for the First Time | Microchip
Co-developing Machine Learning with a RISC-V vector core using Renode for Google Research | Antmicro
Accelerating ML Recommendation With Over 1,000 RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip | David R. Ditzel, Esperanto Technologies Inc
RISC-V Compressed Instructions for SERV | Abdul Wadood, LFX Mentorship at RISC-V InternationalEverything RISC-V at the Design Automation Conference! | RISC-V InternationalProgress in Porting Android onto RISC-V: Android 12 upgrade, vendor modules and TensorFlow Lite | Mao Han, Alibaba CloudPolarFire® SoC FPGA in Conclusive RCHD-PF System Module | Microchip
DeepComputing and Xcalibyte Open Pre-Orders for First Native RISC-V Development Laptop; Quantities Limited | Xcalibyte and Deep Computing
SoC Design Challenge: the first engineering hackathon for students in Russia | Nickolay Ternovoy, Syntacore
Democratizing Chiplet-Based Processor Design | Ventana Micro Systems
RISC-V Vector Processing is Taking Off | SiFive
Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT project
Opening Up New Design Possibilities with OmniXtend
The Cybersecurity Pincushion and a Myriad of Tiny Threat Points
Check out the new RISC-V Careers page and RISC-V Mentorship program!
FOSSi Fever 2020
RISC-V Security Forum 2021 – Schedule Announced!
Growing an Open and Inclusive Community
RISC-V Execution Stages | Maven Silicon
RISC-V Star Rising from the East – Introducing StarFive
RISC-V growth and successes in technology and industry : embedded world 2021
OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IP
RISC-V Becoming Less Risky with the Right Verification
Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT projectOpening Up New Design Possibilities with OmniXtendThe Cybersecurity Pincushion and a Myriad of Tiny Threat PointsCheck out the new RISC-V Careers page and RISC-V Mentorship program!FOSSi Fever 2020RISC-V Security Forum 2021 – Schedule Announced!Growing an Open and Inclusive CommunityRISC-V Execution Stages | Maven SiliconRISC-V Star Rising from the East – Introducing StarFiveRISC-V growth and successes in technology and industry : embedded world 2021OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IPRISC-V Becoming Less Risky with the Right Verification
Architectures for Matrix Extension in CPU | Jiang Zhao, Alibaba CloudRecent rapid development of various applications represented by Deep Learning (DL) calls for a much-needed increase in established chip matrix computing capability. Therefore, CPU manufacturers…
Porting GNOME OS to Microchip’s PolarFire® SoC FPGA Icicle Kit for the First Time | MicrochipCustomers often require support to bring up new boards and architectures on Linux. Our Mi-V ecosystem partner, Codethink’s specialty is board bring-up and they perform…
Co-developing Machine Learning with a RISC-V vector core using Renode for Google Research | AntmicroThe landscape of Machine Learning software libraries and models is evolving rapidly, and to satisfy the ever-increasing demand for memory and compute while managing latency,…
Accelerating ML Recommendation With Over 1,000 RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip | David R. Ditzel, Esperanto Technologies IncMachine learning (ML) recommendation workloads have demanding performance and memory requirements and, to date, have largely been run on servers with x86 processors. To accelerate…
RISC-V Compressed Instructions for SERV | Abdul Wadood, LFX Mentorship at RISC-V InternationalIn Spring 2022, various mentorship projects were offered by RISC-V International on the LFX platform of the Linux Foundation. I got selected for one of…
Everything RISC-V at the Design Automation Conference! | RISC-V InternationalThe Design Automation Conference is here and we're thrilled to share look at all the RISC-V happenings during the show. If you are interested in…
Progress in Porting Android onto RISC-V: Android 12 upgrade, vendor modules and TensorFlow Lite | Mao Han, Alibaba CloudLast year Alibaba T-Head reported that the basic features of Android had been ported onto RISC-V-based Xuantie cores. Since then more effort has been spent…
PolarFire® SoC FPGA in Conclusive RCHD-PF System Module | MicrochipOperational Technology (OT) and Transportation and Industrial Control Systems (ICS) are often forced to make concessions regarding security and updates to deliver critical functionality without…
DeepComputing and Xcalibyte Open Pre-Orders for First Native RISC-V Development Laptop; Quantities Limited | Xcalibyte and Deep ComputingROMA development platform features forthcoming quad-core RISC-V processor for fastest, seamless RISC-V software development experience. DeepComputing and Xcalibyte today opened pre-orders for the industry’s first…
SoC Design Challenge: the first engineering hackathon for students in Russia | Nickolay Ternovoy, SyntacoreYADRO and Syntacore hosted the first ever engineering hackathon for students in Russia. The event was organized in association with National Research University of Electronic…
Democratizing Chiplet-Based Processor Design | Ventana Micro SystemsBy Bob Wheeler, Principal Analyst, The Linley Group Chiplet-based designs promise reduced development costs and faster time to market, but they’ve been exclusive to large…
RISC-V Vector Processing is Taking Off | SiFiveThe RISC-V Vector Extension (RVV) Version 1.0 was ratified by RISC-V International in 2021. Since this public debut, there has been growing excitement about vector…
No recent posts listed
Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT projectThe EU-funded Very Efficient Deep Learning in IoT (VEDLIoT) project is underway. Launched at the end of 2020, it aims to build a next-generation IoT…
Opening Up New Design Possibilities with OmniXtendI am thrilled to see the announcement and initiation of collaboration between CHIPS Alliance and RISC-V International on the OmniXtend Cache Coherency protocol. We have…
The Cybersecurity Pincushion and a Myriad of Tiny Threat Points“Large organizations are using over 130 tools on average. This is just massive!” - Matt Chiodi, CSO, Palo Alto Networks’ public cloud A new Cloud…
Check out the new RISC-V Careers page and RISC-V Mentorship program!We are excited to announce the new RISC-V Careers page and RISC-V Mentorship program! As the RISC-V ecosystem and community grow, we’re bringing together those…
FOSSi Fever 20202020 was a year with a lot of bad news and so it feels slightly strange to cheerfully write about a very specific topic in…
RISC-V Security Forum 2021 – Schedule Announced!The RISC-V Forums, hosted by RISC-V International, are short-form, single-topic, deep-dive virtual events. This is the spirit of RISC-V events - providing technical content to…
Growing an Open and Inclusive CommunityCollaboration underpins everything we do in the RISC-V community. That’s why we encourage everyone to join us and participate, and why we are working hard…
RISC-V Execution Stages | Maven SiliconThis video explains the execution stages of a RISC-V processor and how it executes all the instructions. Follow this RISC-V video blog series to obtain…
RISC-V Star Rising from the East – Introducing StarFiveWith the recent announcement of BeagleVTM, reported by premium technology media Ars Technica, Tom’s Hardware, CNX Software, as well as many others, a new name…
RISC-V growth and successes in technology and industry : embedded world 2021RISC-V International has more than 1,000 members across over 50 countries who are working in hardware, software, services, and various industries for a strong and…
OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IPThe RISC-V ISA (Instruction Set Architecture) permits a range of possibilities for processor implementation with a modular approach for standard and custom extensions. In addition,…
RISC-V Becoming Less Risky with the Right VerificationRISC-V continues to make headlines across the electronic design industry. You may have seen the recent news that the OpenHW Group is delivering their first…
No recent posts listed
Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT projectThe EU-funded Very Efficient Deep Learning in IoT (VEDLIoT) project is underway. Launched at the end of 2020, it aims to build a next-generation IoT…
Opening Up New Design Possibilities with OmniXtendI am thrilled to see the announcement and initiation of collaboration between CHIPS Alliance and RISC-V International on the OmniXtend Cache Coherency protocol. We have…
The Cybersecurity Pincushion and a Myriad of Tiny Threat Points“Large organizations are using over 130 tools on average. This is just massive!” - Matt Chiodi, CSO, Palo Alto Networks’ public cloud A new Cloud…
Check out the new RISC-V Careers page and RISC-V Mentorship program!We are excited to announce the new RISC-V Careers page and RISC-V Mentorship program! As the RISC-V ecosystem and community grow, we’re bringing together those…
FOSSi Fever 20202020 was a year with a lot of bad news and so it feels slightly strange to cheerfully write about a very specific topic in…
RISC-V Security Forum 2021 – Schedule Announced!The RISC-V Forums, hosted by RISC-V International, are short-form, single-topic, deep-dive virtual events. This is the spirit of RISC-V events - providing technical content to…
Growing an Open and Inclusive CommunityCollaboration underpins everything we do in the RISC-V community. That’s why we encourage everyone to join us and participate, and why we are working hard…
RISC-V Execution Stages | Maven SiliconThis video explains the execution stages of a RISC-V processor and how it executes all the instructions. Follow this RISC-V video blog series to obtain…
RISC-V Star Rising from the East – Introducing StarFiveWith the recent announcement of BeagleVTM, reported by premium technology media Ars Technica, Tom’s Hardware, CNX Software, as well as many others, a new name…
RISC-V growth and successes in technology and industry : embedded world 2021RISC-V International has more than 1,000 members across over 50 countries who are working in hardware, software, services, and various industries for a strong and…
OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IPThe RISC-V ISA (Instruction Set Architecture) permits a range of possibilities for processor implementation with a modular approach for standard and custom extensions. In addition,…
RISC-V Becoming Less Risky with the Right VerificationRISC-V continues to make headlines across the electronic design industry. You may have seen the recent news that the OpenHW Group is delivering their first…