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GreenWaves will Demonstrate Live the Ground-breaking AI and DSP Demos on its Ultra Low Power Chip at Embedded World 2022 | GreenWaves Technologies
Overtake the Competition in Automotive Design with RISC-V Innovations | Codasip
RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021 | RISC-V International
Renode 1.13 for improved machine learning and pre-silicon development | Antmicro
Thermal (IR) Imaging Pipeline (ISP) Core on PolarFire® SoC FPGA SoM | Microchip
XuanTie C906 Tops MLPerf Tiny v0.7 Benchmark | MengChang, Alibaba Cloud
Why MIPS is Betting Big on RISC-V: Q&A with RISC-V International and MIPS | MIPS
RISC-V Summit China 2022 Call for Talks is Now OpenSimplifying the Vehicle to Anything (V2X) Journey: Porting of Jamaica VM on PolarFire® SoC Icicle Kit | Leah Iris, MicrochipMIPS Pivots to RISC-V with Best-In-Class Performance and Scalability | MIPS
E4 Computer Engineering joins RISC-V International | E4 Computer Engineering
RISC-V Open Era of Computing – A Conversation with Calista Redmond and Mr. Sivakumar P R , Founder and CEO of Maven Silicon | Maven Silicon
High-throughput open source PCIe on Xilinx VU19P-based ASIC prototyping platform
Hardware Description Language Chisel & Diplomacy Deeper dive
Where to start with RISC-VOverview of Diplomacy for writing effective hardware design language Chisel (Japanese)
RISC-V CPU Performance | Maven Silicon
Let’s Make RISC-V Connected Systems Synonymous with Security
RISC-V Microarchitecture for Kids??!! | Steve Hoover, Redwood EDA
What is Processor Core Complexity?
What is Needed to Support an Operating System?
Understanding the Performance of Processor IP Cores
RPC DRAM support in open source DRAM controller
13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core
High-throughput open source PCIe on Xilinx VU19P-based ASIC prototyping platformHardware Description Language Chisel & Diplomacy Deeper diveWhere to start with RISC-VOverview of Diplomacy for writing effective hardware design language Chisel (Japanese)RISC-V CPU Performance | Maven SiliconLet’s Make RISC-V Connected Systems Synonymous with SecurityRISC-V Microarchitecture for Kids??!! | Steve Hoover, Redwood EDAWhat is Processor Core Complexity?What is Needed to Support an Operating System?Understanding the Performance of Processor IP CoresRPC DRAM support in open source DRAM controller13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core
GreenWaves will Demonstrate Live the Ground-breaking AI and DSP Demos on its Ultra Low Power Chip at Embedded World 2022 | GreenWaves TechnologiesLocated in the micro-and nano-electronics hotspot of Grenoble, GreenWaves is a fabless semiconductor startup that designs and brings to market advanced ultra-low-power AI and DSP…
Overtake the Competition in Automotive Design with RISC-V Innovations | CodasipIn conversation with Jamie Broome, Codasip VP of Automotive Jamie Broome recently joined Codasip as VP Automotive with more than 20 years of semiconductor…
RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021 | RISC-V InternationalEfficient Trace, Supervisor Binary Interface, Unified Extensible Firmware Interface, and Zmmul Multiply-Only Extension Accelerate Embedded- and Large-System Design. Six Additional Specifications Already In the Pipeline…
Renode 1.13 for improved machine learning and pre-silicon development | AntmicroAfter a longer while, we are excited to announce that the next release of Renode is here. Since the previous release we’ve been busy working with many…
Thermal (IR) Imaging Pipeline (ISP) Core on PolarFire® SoC FPGA SoM | MicrochipOur Mi-V partner, Digital Core Technologies (DCT), has developed a thermal Imaging Pipeline on PolarFire® SoC FPGA. The thermal Image Signal Processor (ISP) is an…
XuanTie C906 Tops MLPerf Tiny v0.7 Benchmark | MengChang, Alibaba CloudXuanTie C906 is a processor developed by Alibaba Cloud based on the RISC-V instruction set architecture. It has attained top marks in the most recent…
Why MIPS is Betting Big on RISC-V: Q&A with RISC-V International and MIPS | MIPSMIPS recently announced that the company is pivoting to RISC-V and introduced its first MIPS products based on RISC-V, targeting automotive, 5G and wireless networking,…
RISC-V Summit China 2022 Call for Talks is Now OpenThe RISC-V Summit China 2022 will showcase the continued rapid expansion of the RISC-V ecosystem, with both commercial offerings and exciting open-source developments. The event will…
Simplifying the Vehicle to Anything (V2X) Journey: Porting of Jamaica VM on PolarFire® SoC Icicle Kit | Leah Iris, MicrochipIndustries like manufacturing and automotive are facing the challenges of getting access to device-wide data, analyzing useful data and combining and processing data in the…
MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability | MIPSMIPS previews the first IP solutions in the eVocore™ product lineup: P8700 and I8500 multiprocessors. SAN JOSE, Calif., May 10, 2022 /PRNewswire/ -- MIPS, a leading developer of…
E4 Computer Engineering joins RISC-V International | E4 Computer EngineeringThe company aims to promote the development and application of the RISC-V open standard in ecosystems for HPC applications. Scandiano (RE), May 3rd 2022…
RISC-V Open Era of Computing – A Conversation with Calista Redmond and Mr. Sivakumar P R , Founder and CEO of Maven Silicon | Maven SiliconIndia’s top VLSI Training Services company Maven Silicon, a RISC-V Global Training Partner, conducted an insightful discussion with the industry experts Ms. Calista Redmond, CEO,…
No recent posts listed
High-throughput open source PCIe on Xilinx VU19P-based ASIC prototyping platformOriginally published by Antmicro In the daily work at Antmicro, they use FPGAs primarily for their flexibility and parallel data processing capabilities that make…
Hardware Description Language Chisel & Diplomacy Deeper diveAre you using Chisel? A hardware building language based on Scala. Not a high-level synthesis language. SiFive's RISC-V IP use Chisel Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom…
Where to start with RISC-VOriginally posted on Medium How to get started, where to contribute, and what to do next RISC-V made the news recently when BeagleBoard.org revealed the…
Overview of Diplomacy for writing effective hardware design language Chisel (Japanese)ハードウェア記述言語Chiselをもっともっと活用するためのDiplomacy概説 発表者：msyksphinz (FPGA開発日記著者) @msyksphinz_dev https://msyksphinz.hatenablog.com Chisel使ってますか？ Scalaをベースとしたハードウェア構築言語. 高位合成言語ではない SiFiveのRISC-V IPで採用されている Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom Chiselの基礎 : 「Chiselを始めたい人に読んで欲しい本」 https://nextpublishing.jp/book/12162.html ChiselがVerilogを生成するまで ChiselはScalaのDSLなので、Chisel CompilerはScalaで記述してある Chisel CompilerはFIR (Flexible Interpretation Representation)と呼ばれる中間言語を生成する…
RISC-V CPU Performance | Maven SiliconThis video explains how Maven Silicon measures the CPU performance and how we try to improve the processor performance by improving its clock frequency and…
Let’s Make RISC-V Connected Systems Synonymous with SecurityThis blog was submitted by Silex Insight. If you are designing systems based on a RISC-V architecture, for example to run highly connected applications,…
RISC-V Microarchitecture for Kids??!! | Steve Hoover, Redwood EDALast month I had the great pleasure of sharing a blog post about Nicholas Sharkey, an amazing 13 year-old who participated with graduate students and…
What is Processor Core Complexity?This blog was originally published on the Codasip blog. The more complex a processor core, the larger the area and power consumption. But increasing…
What is Needed to Support an Operating System?This blog was originally published on the Codasip blog. For each embedded product, software developers need to consider whether they need an operating system;…
Understanding the Performance of Processor IP CoresThis blog was originally published on the Codasip blog. Looking at any processor IP, you will find that their vendors emphasise PPA (performance, power…
RPC DRAM support in open source DRAM controllerOriginal content published October 28, 2020 on the Antmicro blog. The Internet of Things is one of the areas that is hugely benefiting from miniaturization…
13-Year-Old, Nicholas Sharkey, Creates a RISC-V CoreOne of my great pleasures operating my EDA startup, Redwood EDA, is working with enthusiastic college students and open-source developers and seeing how our technology…
No recent posts listed
High-throughput open source PCIe on Xilinx VU19P-based ASIC prototyping platformOriginally published by Antmicro In the daily work at Antmicro, they use FPGAs primarily for their flexibility and parallel data processing capabilities that make…
Hardware Description Language Chisel & Diplomacy Deeper diveAre you using Chisel? A hardware building language based on Scala. Not a high-level synthesis language. SiFive's RISC-V IP use Chisel Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom…
Where to start with RISC-VOriginally posted on Medium How to get started, where to contribute, and what to do next RISC-V made the news recently when BeagleBoard.org revealed the…
Overview of Diplomacy for writing effective hardware design language Chisel (Japanese)ハードウェア記述言語Chiselをもっともっと活用するためのDiplomacy概説 発表者：msyksphinz (FPGA開発日記著者) @msyksphinz_dev https://msyksphinz.hatenablog.com Chisel使ってますか？ Scalaをベースとしたハードウェア構築言語. 高位合成言語ではない SiFiveのRISC-V IPで採用されている Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom Chiselの基礎 : 「Chiselを始めたい人に読んで欲しい本」 https://nextpublishing.jp/book/12162.html ChiselがVerilogを生成するまで ChiselはScalaのDSLなので、Chisel CompilerはScalaで記述してある Chisel CompilerはFIR (Flexible Interpretation Representation)と呼ばれる中間言語を生成する…
RISC-V CPU Performance | Maven SiliconThis video explains how Maven Silicon measures the CPU performance and how we try to improve the processor performance by improving its clock frequency and…
Let’s Make RISC-V Connected Systems Synonymous with SecurityThis blog was submitted by Silex Insight. If you are designing systems based on a RISC-V architecture, for example to run highly connected applications,…
RISC-V Microarchitecture for Kids??!! | Steve Hoover, Redwood EDALast month I had the great pleasure of sharing a blog post about Nicholas Sharkey, an amazing 13 year-old who participated with graduate students and…
What is Processor Core Complexity?This blog was originally published on the Codasip blog. The more complex a processor core, the larger the area and power consumption. But increasing…
What is Needed to Support an Operating System?This blog was originally published on the Codasip blog. For each embedded product, software developers need to consider whether they need an operating system;…
Understanding the Performance of Processor IP CoresThis blog was originally published on the Codasip blog. Looking at any processor IP, you will find that their vendors emphasise PPA (performance, power…
RPC DRAM support in open source DRAM controllerOriginal content published October 28, 2020 on the Antmicro blog. The Internet of Things is one of the areas that is hugely benefiting from miniaturization…
13-Year-Old, Nicholas Sharkey, Creates a RISC-V CoreOne of my great pleasures operating my EDA startup, Redwood EDA, is working with enthusiastic college students and open-source developers and seeing how our technology…