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Open source System on Module with Microchip PolarFire SoC

The PolarFire SoC was the world’s first Linux-enabled mass market multi-core RISC-V SoC, originally made available pre-silicon by Microchip through Antmicro’s Renode simulation framework. Thanks…

[VIDEO] Developing the RISC-V Framework Laptop Mainboard

Nirav & Hyelim sit down at Framework HQ SF to talk about all things RISC-V and DeepComputing. RISC-V Mainboard: https://frame.work/products/deep-comp... Read the blog post: https://frame.work/blog/introducing-a...…

Canonical Adds Microchip’s New PIC64GX to Its List of Ubuntu-Supported RISC-V Platforms

Canonical has announced another new entry in its growing list of RISC-V platforms for which an official Ubuntu Linux image is available, launching an image…

Defining RISC-V CPUs in Renode simulation with custom instructions and extensions

By: Antmicro The openness and customizability of the RISC-V ISA has encouraged its use across a variety of scenarios, such as supporting cores in larger…

Debugging of RISC-V-Based Chips Made Easy

FROM SIMPLE MICROCONTROLLERS TO COMPLEX MULTICORE SOCS RISC-V cores can be found in increasingly more chips, either as the main CPU(s) or as a companion…

Leveraging Safety Processor Expertise to Develop RISC-V Based Automotive Implementations

The podcast interview explores the role of RISC-V in the automotive sector. It begins with a brief introduction to RISC-V, explaining it as an open standard…

Wuhan Sets Up Open-Source RISC-V Innovation Hub for Next-Gen Chips

(Yicai) July 26 -- Central Chinese city of Wuhan has formed a new innovation hub for RISC-V, an open-source instruction set architecture used to design…

Lauterbach Supports Microchip’s PIC64GX RISC-V® MPUs

Hoehenkirchen, Germany—July 25, 2024 — Lauterbach’s TRACE32® development tools now support Microchip’s 64-bit RISC-V® PIC64GX microprocessor family for power-efficient embedded-compute platforms. TRACE32® tools support includes…

New Launch: Advanced RISC-V Courses | Maven Silicon

By: Maven Silicon We are delighted to inform you that we have recently published Advanced RISC-V Processor IP Design and Verification Online Courses. Our Founder and…

Ashling announces RiscFree™ C/C++ SDK support for Microchip Technologies’ PIC64GX RISC-V ® -based multicore MPUs

July-23rd , 2024, Limerick, Ireland. Embedded tools developer Ashling is pleased to partner with Microchip Technology, supporting the new and innovative PIC64GX RISC-V based multicore…

Imagination Technologies announces new capital investment from Fortress Investment Group

Imagination Technologies (“Imagination”) today announced a new investment by funds managed by affiliates of Fortress Investment Group LLC (“Fortress”).  Under the terms of the agreement, Fortress…

How ChipFlow is Making the Impossible Possible

With Innovative technology, a collaborative spirit and a unique value proposition, Chip flow is setting itself to be the next generation of semiconductor solutions. Interview…

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Cooperation and Competition Behind the Scenes in the RISC-V Community

RISC-V “is changing the way people build every single computer,” says Mark Himelstein, the former CTO at RISC-V International. He joins us to explain the…

Here’s why RISC-V is so important

RISC-V has been an industry buzzword over the last few years, making waves with a range of wacky devices and chips from all sorts of manufacturers.…

[VIDEO] Applications for the RISC-V Revolution – The Electropages Podcast with Bluespec, Inc

Welcome to another episode of the Electropages podcast. Today, host Robin Mitchell is joined by Charlie Hauck, CEO of Bluespec Inc, to explore the latest…

Compiler toolset for RISC-V in safety and security-critical automotive applications

TASKING has introduced the new compiler toolset VX-Toolset for RISC-V. The industry's first ISO 26262 and ISO/SAE 21434 compliant compiler enables the development of automotive…

A Striped Bus Architecture for Minimizing Multi-Core Interference

Understanding the intricacies of software timing behaviour is crucial, especially in safety-critical systems and systems with real-time requirements. While analysing timing on single-core processor architecture…

SYSGO Supports RISC-V with its Embedded Linux ELinOS Version 7.2

SYSGO released its support for RISC-V via its embedded Linux ELinOS version 7.2. The platform fully supports Microchip's PolarFire SoC Icicle. The ratification also sees…

RISC-V: Democratizing Innovation in CPU Design

RISC-V has emerged as a groundbreaking force in the semiconductor industry, fundamentally changing the CPU design and manufacturing landscape. By providing an open standard instruction…

BSC and Brazil’s Instituto ELDORADO Collaborate to Advance RISC-V Development for HPC and AI

An international collaboration between BSC and Instituto ELDORADO will enable Brazil to develop open-source RISC-V technologies to accelerate research and development in the areas of semiconductors and supercomputing. The…

IoT & Embedded Technology Report

Embedded World 2024 proved that the industry is becoming more competitive as rapid innovations emerge across a number of different sectors and elements of the…

High Degree of Specification Activity Helps with Further RISC-V Adoption

RISC-V International has succeeded in ratifying 40 new technical specifications relating to the RISC-V instruction set architecture (ISA) over the course of the last 2…

Unlocking the future of India’s semiconductor landscape with RISC-V Innovation

In recent years, India's semiconductor industry has witnessed remarkable growth and innovation, fueled by a combination of several innovations, strategic partnerships, and technological advancements. At…

Enhancing the RISC-V Ecosystem with S2C Prototyping Solution

RISC-V’s popularity stems from its open-source framework, enabling customization, scalability, and mitigating vendor lock-in. Supported by a robust community, its cost-effectiveness and global adoption make…