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Debugging of RISC-V-Based Chips Made Easy
Leveraging Safety Processor Expertise to Develop RISC-V Based Automotive Implementations
Wuhan Sets Up Open-Source RISC-V Innovation Hub for Next-Gen Chips
Lauterbach Supports Microchip’s PIC64GX RISC-V® MPUs
New Launch: Advanced RISC-V Courses | Maven Silicon
Ashling announces RiscFree™ C/C++ SDK support for Microchip Technologies’ PIC64GX RISC-V ® -based multicore MPUs
Imagination Technologies announces new capital investment from Fortress Investment Group
How ChipFlow is Making the Impossible Possible
Microchip Unveils Industry’s Highest Performance 64-bit HPSC Microprocessor (MPU) Family for a New Era of Autonomous Space ComputingAshling announces RiscFree™ C/C++ SDK support for India’s C-DAC VEGA RISC-V-based Multi-core MicroprocessorsTrillions of Cycles per Day: How SiFive Boosts IP and Software Validation with Synopsys HAPS Prototyping SystemHow Early Power Analysis Drives Energy-Efficient RISC-V Designs
Here’s why RISC-V is so important[VIDEO] Applications for the RISC-V Revolution – The Electropages Podcast with Bluespec, Inc
Compiler toolset for RISC-V in safety and security-critical automotive applications
A Striped Bus Architecture for Minimizing Multi-Core InterferenceSYSGO Supports RISC-V with its Embedded Linux ELinOS Version 7.2
RISC-V: Democratizing Innovation in CPU DesignBSC and Brazil’s Instituto ELDORADO Collaborate to Advance RISC-V Development for HPC and AIIoT & Embedded Technology ReportHigh Degree of Specification Activity Helps with Further RISC-V AdoptionUnlocking the future of India’s semiconductor landscape with RISC-V Innovation
Enhancing the RISC-V Ecosystem with S2C Prototyping SolutionVentana and Canonical collaborate on enabling enterprise data center, high-performance and AI computing on RISC-V
Debugging of RISC-V-Based Chips Made EasyFROM SIMPLE MICROCONTROLLERS TO COMPLEX MULTICORE SOCS RISC-V cores can be found in increasingly more chips, either as the main CPU(s) or as a companion…
Leveraging Safety Processor Expertise to Develop RISC-V Based Automotive ImplementationsThe podcast interview explores the role of RISC-V in the automotive sector. It begins with a brief introduction to RISC-V, explaining it as an open standard…
Wuhan Sets Up Open-Source RISC-V Innovation Hub for Next-Gen Chips(Yicai) July 26 -- Central Chinese city of Wuhan has formed a new innovation hub for RISC-V, an open-source instruction set architecture used to design…
Lauterbach Supports Microchip’s PIC64GX RISC-V® MPUsHoehenkirchen, Germany—July 25, 2024 — Lauterbach’s TRACE32® development tools now support Microchip’s 64-bit RISC-V® PIC64GX microprocessor family for power-efficient embedded-compute platforms. TRACE32® tools support includes…
New Launch: Advanced RISC-V Courses | Maven SiliconBy: Maven Silicon We are delighted to inform you that we have recently published Advanced RISC-V Processor IP Design and Verification Online Courses. Our Founder and…
Ashling announces RiscFree™ C/C++ SDK support for Microchip Technologies’ PIC64GX RISC-V ® -based multicore MPUsJuly-23rd , 2024, Limerick, Ireland. Embedded tools developer Ashling is pleased to partner with Microchip Technology, supporting the new and innovative PIC64GX RISC-V based multicore…
Imagination Technologies announces new capital investment from Fortress Investment GroupImagination Technologies (“Imagination”) today announced a new investment by funds managed by affiliates of Fortress Investment Group LLC (“Fortress”). Under the terms of the agreement, Fortress…
How ChipFlow is Making the Impossible PossibleWith Innovative technology, a collaborative spirit and a unique value proposition, Chip flow is setting itself to be the next generation of semiconductor solutions. Interview…
Microchip Unveils Industry’s Highest Performance 64-bit HPSC Microprocessor (MPU) Family for a New Era of Autonomous Space ComputingCHANDLER, Ariz., JULY 9, 2024 — The world has changed dramatically in the two decades since the debut of what was then considered a trail-blazing space-grade…
Ashling announces RiscFree™ C/C++ SDK support for India’s C-DAC VEGA RISC-V-based Multi-core MicroprocessorsJuly-8 th, 2024, Kochi, India. Embedded tools developer Ashling is pleased to partner with C-DAC, supporting their VEGA RISC-V based multi-core microprocessor family with our…
Trillions of Cycles per Day: How SiFive Boosts IP and Software Validation with Synopsys HAPS Prototyping SystemIn today’s landscape of generative AI, IoT, and more, the demand for advanced RISC-V core IP is rapidly escalating. As technology becomes increasingly software-driven, the…
How Early Power Analysis Drives Energy-Efficient RISC-V DesignsIn the world of processor development, flexibility is becoming a distinct advantage. As an open-standard instruction set architecture (ISA), the fifth iteration of reduced instruction…
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Here’s why RISC-V is so importantRISC-V has been an industry buzzword over the last few years, making waves with a range of wacky devices and chips from all sorts of manufacturers.…
[VIDEO] Applications for the RISC-V Revolution – The Electropages Podcast with Bluespec, IncWelcome to another episode of the Electropages podcast. Today, host Robin Mitchell is joined by Charlie Hauck, CEO of Bluespec Inc, to explore the latest…
Compiler toolset for RISC-V in safety and security-critical automotive applicationsTASKING has introduced the new compiler toolset VX-Toolset for RISC-V. The industry's first ISO 26262 and ISO/SAE 21434 compliant compiler enables the development of automotive…
A Striped Bus Architecture for Minimizing Multi-Core InterferenceUnderstanding the intricacies of software timing behaviour is crucial, especially in safety-critical systems and systems with real-time requirements. While analysing timing on single-core processor architecture…
SYSGO Supports RISC-V with its Embedded Linux ELinOS Version 7.2SYSGO released its support for RISC-V via its embedded Linux ELinOS version 7.2. The platform fully supports Microchip's PolarFire SoC Icicle. The ratification also sees…
RISC-V: Democratizing Innovation in CPU DesignRISC-V has emerged as a groundbreaking force in the semiconductor industry, fundamentally changing the CPU design and manufacturing landscape. By providing an open standard instruction…
BSC and Brazil’s Instituto ELDORADO Collaborate to Advance RISC-V Development for HPC and AIAn international collaboration between BSC and Instituto ELDORADO will enable Brazil to develop open-source RISC-V technologies to accelerate research and development in the areas of semiconductors and supercomputing. The…
IoT & Embedded Technology ReportEmbedded World 2024 proved that the industry is becoming more competitive as rapid innovations emerge across a number of different sectors and elements of the…
High Degree of Specification Activity Helps with Further RISC-V AdoptionRISC-V International has succeeded in ratifying 40 new technical specifications relating to the RISC-V instruction set architecture (ISA) over the course of the last 2…
Unlocking the future of India’s semiconductor landscape with RISC-V InnovationIn recent years, India's semiconductor industry has witnessed remarkable growth and innovation, fueled by a combination of several innovations, strategic partnerships, and technological advancements. At…
Enhancing the RISC-V Ecosystem with S2C Prototyping SolutionRISC-V’s popularity stems from its open-source framework, enabling customization, scalability, and mitigating vendor lock-in. Supported by a robust community, its cost-effectiveness and global adoption make…
Ventana and Canonical collaborate on enabling enterprise data center, high-performance and AI computing on RISC-VRISC-V, an open standard instruction set architecture (ISA), is rapidly shaping the future of high-performance computing, edge computing, and artificial intelligence. The RISC-V customizable and…