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Microchip, and O.C.E. Technology deliver high-reliability RTOS for Polarfire® SoC FPGA space applications
Raspberry Pi Launch New RP2350 Microcontroller and Pico 2 Development Board with RISC-V Support
RISC-V 中国峰会议程初版已在官网公布，8月12日形成最终版
Open source System on Module with Microchip PolarFire SoC
[VIDEO] Developing the RISC-V Framework Laptop MainboardCanonical Adds Microchip’s New PIC64GX to Its List of Ubuntu-Supported RISC-V PlatformsDefining RISC-V CPUs in Renode simulation with custom instructions and extensions
Debugging of RISC-V-Based Chips Made Easy
Leveraging Safety Processor Expertise to Develop RISC-V Based Automotive ImplementationsWuhan Sets Up Open-Source RISC-V Innovation Hub for Next-Gen Chips
Lauterbach Supports Microchip’s PIC64GX RISC-V® MPUs
New Launch: Advanced RISC-V Courses | Maven Silicon
Here’s why RISC-V is so important[VIDEO] Applications for the RISC-V Revolution – The Electropages Podcast with Bluespec, Inc
Compiler toolset for RISC-V in safety and security-critical automotive applications
A Striped Bus Architecture for Minimizing Multi-Core InterferenceSYSGO Supports RISC-V with its Embedded Linux ELinOS Version 7.2
RISC-V: Democratizing Innovation in CPU DesignBSC and Brazil’s Instituto ELDORADO Collaborate to Advance RISC-V Development for HPC and AIIoT & Embedded Technology ReportHigh Degree of Specification Activity Helps with Further RISC-V AdoptionUnlocking the future of India’s semiconductor landscape with RISC-V Innovation
Enhancing the RISC-V Ecosystem with S2C Prototyping SolutionVentana and Canonical collaborate on enabling enterprise data center, high-performance and AI computing on RISC-V
Microchip, and O.C.E. Technology deliver high-reliability RTOS for Polarfire® SoC FPGA space applicationsBy: Barry Kavanagh, Chief Executive Officer, O.C.E. Technology Ltd. Polarfire® SoC FPGA RISC-V space applications can now take advantage of an RTOS compliant to ESA…
Raspberry Pi Launch New RP2350 Microcontroller and Pico 2 Development Board with RISC-V SupportRaspberry Pi is one of the most recognisable brands of single board computers, created as an affordable way to promote the teaching of computer science…
RISC-V 中国峰会议程初版已在官网公布，8月12日形成最终版经过 2024 RISC-V 中国峰会程序委员会两轮投稿评审，2024 RISC-V 中国峰会的演讲议程已经初步完成，并在中国峰会的官网公布： https://riscv-summit-china.com/agenda/ 本次峰会共接收了超过120个演讲、30篇POSTER投稿；超过15场同期活动将在8月19-25日同步进行。预计会有超过百家企业、研究机构、高校及开源社区的开发者在峰会和同期活动会场上分享交流 RISC-V 领域的最新成果。 请注意目前的议程并未最终版本，演讲信息是根据2024年6月22日及7月18日两轮投稿信息整理，部分演讲的标题和演讲者信息会在8月10-12日左右进行更新完善，请以 RISC-V 中国峰会官网更新为准。 媒体联系（中文）： 张女士 zhangyuxi@iscas.ac.cn 媒体联系（英文）：china@riscv.org
Open source System on Module with Microchip PolarFire SoCThe PolarFire SoC was the world’s first Linux-enabled mass market multi-core RISC-V SoC, originally made available pre-silicon by Microchip through Antmicro’s Renode simulation framework. Thanks…
[VIDEO] Developing the RISC-V Framework Laptop MainboardNirav & Hyelim sit down at Framework HQ SF to talk about all things RISC-V and DeepComputing. RISC-V Mainboard: https://frame.work/products/deep-comp... Read the blog post: https://frame.work/blog/introducing-a...…
Canonical Adds Microchip’s New PIC64GX to Its List of Ubuntu-Supported RISC-V PlatformsCanonical has announced another new entry in its growing list of RISC-V platforms for which an official Ubuntu Linux image is available, launching an image…
Defining RISC-V CPUs in Renode simulation with custom instructions and extensionsBy: Antmicro The openness and customizability of the RISC-V ISA has encouraged its use across a variety of scenarios, such as supporting cores in larger…
Debugging of RISC-V-Based Chips Made EasyFROM SIMPLE MICROCONTROLLERS TO COMPLEX MULTICORE SOCS RISC-V cores can be found in increasingly more chips, either as the main CPU(s) or as a companion…
Leveraging Safety Processor Expertise to Develop RISC-V Based Automotive ImplementationsThe podcast interview explores the role of RISC-V in the automotive sector. It begins with a brief introduction to RISC-V, explaining it as an open standard…
Wuhan Sets Up Open-Source RISC-V Innovation Hub for Next-Gen Chips(Yicai) July 26 -- Central Chinese city of Wuhan has formed a new innovation hub for RISC-V, an open-source instruction set architecture used to design…
Lauterbach Supports Microchip’s PIC64GX RISC-V® MPUsHoehenkirchen, Germany—July 25, 2024 — Lauterbach’s TRACE32® development tools now support Microchip’s 64-bit RISC-V® PIC64GX microprocessor family for power-efficient embedded-compute platforms. TRACE32® tools support includes…
New Launch: Advanced RISC-V Courses | Maven SiliconBy: Maven Silicon We are delighted to inform you that we have recently published Advanced RISC-V Processor IP Design and Verification Online Courses. Our Founder and…
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Here’s why RISC-V is so importantRISC-V has been an industry buzzword over the last few years, making waves with a range of wacky devices and chips from all sorts of manufacturers.…
[VIDEO] Applications for the RISC-V Revolution – The Electropages Podcast with Bluespec, IncWelcome to another episode of the Electropages podcast. Today, host Robin Mitchell is joined by Charlie Hauck, CEO of Bluespec Inc, to explore the latest…
Compiler toolset for RISC-V in safety and security-critical automotive applicationsTASKING has introduced the new compiler toolset VX-Toolset for RISC-V. The industry's first ISO 26262 and ISO/SAE 21434 compliant compiler enables the development of automotive…
A Striped Bus Architecture for Minimizing Multi-Core InterferenceUnderstanding the intricacies of software timing behaviour is crucial, especially in safety-critical systems and systems with real-time requirements. While analysing timing on single-core processor architecture…
SYSGO Supports RISC-V with its Embedded Linux ELinOS Version 7.2SYSGO released its support for RISC-V via its embedded Linux ELinOS version 7.2. The platform fully supports Microchip's PolarFire SoC Icicle. The ratification also sees…
RISC-V: Democratizing Innovation in CPU DesignRISC-V has emerged as a groundbreaking force in the semiconductor industry, fundamentally changing the CPU design and manufacturing landscape. By providing an open standard instruction…
BSC and Brazil’s Instituto ELDORADO Collaborate to Advance RISC-V Development for HPC and AIAn international collaboration between BSC and Instituto ELDORADO will enable Brazil to develop open-source RISC-V technologies to accelerate research and development in the areas of semiconductors and supercomputing. The…
IoT & Embedded Technology ReportEmbedded World 2024 proved that the industry is becoming more competitive as rapid innovations emerge across a number of different sectors and elements of the…
High Degree of Specification Activity Helps with Further RISC-V AdoptionRISC-V International has succeeded in ratifying 40 new technical specifications relating to the RISC-V instruction set architecture (ISA) over the course of the last 2…
Unlocking the future of India’s semiconductor landscape with RISC-V InnovationIn recent years, India's semiconductor industry has witnessed remarkable growth and innovation, fueled by a combination of several innovations, strategic partnerships, and technological advancements. At…
Enhancing the RISC-V Ecosystem with S2C Prototyping SolutionRISC-V’s popularity stems from its open-source framework, enabling customization, scalability, and mitigating vendor lock-in. Supported by a robust community, its cost-effectiveness and global adoption make…
Ventana and Canonical collaborate on enabling enterprise data center, high-performance and AI computing on RISC-VRISC-V, an open standard instruction set architecture (ISA), is rapidly shaping the future of high-performance computing, edge computing, and artificial intelligence. The RISC-V customizable and…