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SiFive Essential Product Family Expanded at the RISC-V Summit Europe
RISC-V Verification: From Simulation To FormalSiFive announces 4th-gen of popular essential product line to spur innovation across embedded applications
Accelerate RISC-V Verification Using Synopsys CloudAccelerate RISC-V Verification Using Synopsys Cloud
Developers Use RISC-V Stack Without Worrying About Local SRAMs, DMAsESWIN Computing Pairs SiFive CPU, Imagination GPU and In House NPU in Latest RISC-V Edge Computing SoCRISC-V Summit: SiFive’s 4th generation embedded cores
DAC 2024 Day One: Designing Chiplets and AI with RISC-VSemidynamics benchmarks 7bn parameter model on RISC-V AI IP
X-Silicon Introduces the World’s First Vulkan Driver Implementation for RISC-V, Enabling an entire Ecosystem of 3D Graphics, AI and Compute for Low-Power, Mobile, Edge and IOT Devices
RISC-V Summit Europe is Underway with 700+ Attendees Representing 40 Countries
Tenstorrent and MosChip Partner on High Performant RISC-V Design
embedded world 2024: Codasip demonstrates CHERI memory protectionPeople to Watch 2024 – Calista RedmondAndes Technology: Cultivating Academic Collaboration for Over a Decade with Sustainable SpiritWhat is RISC-V and Why Has it Become Important for Java?Tiempo Secure announces TESIC RISC-V Secure Element IP and development kit
Here’s Your Sneak Peek at SNUG Silicon Valley 2024Next Euro HPC Chip Coming Next Year Will Be in 2026 EU Exascale System[VIDEO] RISC-V for Edge AI ApplicationsFrom vision to reality in RISC-V: Interview with Karel MasarikHow the RISC-V ISA Offers Greater Design Freedom and FlexibilityUnderstanding RISC-V: The Open Standard Instruction Set Architecture
SiFive Essential Product Family Expanded at the RISC-V Summit EuropeMunich, Germany. SiFive, Inc. announced an innovative design of its SiFive Essential product family at the RISC-V Summit Europe 2024. With over a decade of development,…
RISC-V Verification: From Simulation To FormalAxiomise’s Nicky Khodadad and Ashish Darbari discuss simulation and the need for formal verification and RISC-V, including why simulation-based verification is inadequate to find all…
SiFive announces 4th-gen of popular essential product line to spur innovation across embedded applicationsSiFive is seeing growing adoption, with more than two billion SiFive RISC-V-based chips already in the market. SiFive, Inc. the gold standard for RISC-V computing,…
Accelerate RISC-V Verification Using Synopsys CloudRISC-V is an emerging choice for semiconductor companies to create highly differentiated products for a wide range of end applications. Both established players and start-up…
Accelerate RISC-V Verification Using Synopsys CloudRISC-V is an emerging choice for semiconductor companies to create highly differentiated products for a wide range of end applications. Both established players and start-up…
Developers Use RISC-V Stack Without Worrying About Local SRAMs, DMAsSemidynamics Tensor Unit efficiency data for its “All-In-One” AI IP, which uses a LlaMA-2 7B-parameter Large Language Model (LLM), has been made public. Roger Espasa,…
ESWIN Computing Pairs SiFive CPU, Imagination GPU and In House NPU in Latest RISC-V Edge Computing SoCCombining IP from two RISC-V leaders with an independently developed NPU brings advanced AI acceleration and rich user interfaces to ESWIN Computing’s EIC77 Series SoCs.…
RISC-V Summit: SiFive’s 4th generation embedded coresSiFive announced the 4th generation of RISC-V CPU cores for embedded applications at RISC-V Summit Europe 2024 today. There are eight cores, three of which…
DAC 2024 Day One: Designing Chiplets and AI with RISC-VWatch the first of our roundups from DAC 2024, taking place this week at the Moscone Center in San Francisco, where we talk about the…
Semidynamics benchmarks 7bn parameter model on RISC-V AI IPSpanish RISC-V IP developer Semidynamics has benchmarked the performance of its Tensor Unit running a LlaMA-2 7B-parameter Large Language Model (LLM) on an ‘all in…
X-Silicon Introduces the World’s First Vulkan Driver Implementation for RISC-V, Enabling an entire Ecosystem of 3D Graphics, AI and Compute for Low-Power, Mobile, Edge and IOT DevicesSAN DIEGO, June 25, 2024 /PRNewswire/ -- X-Silicon is demonstrating the 1st Vulkan™ Software Rendering Platform capability running on the RISC-V Architecture. This opens up…
RISC-V Summit Europe is Underway with 700+ Attendees Representing 40 CountriesThis year’s RISC-V Summit Europe, taking place in Munich, Germany from Monday, June 24 – Friday, June 28, has already welcomed more than 700 attendees…
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Tenstorrent and MosChip Partner on High Performant RISC-V DesignSANTA CLARA, Calif., March 13, 2024 /PRNewswire/ --Tenstorrent and MosChip Technologies announced today that they are partnering on design for Tenstorrent's cutting-edge RISC-V solutions. In selecting MosChip…
embedded world 2024: Codasip demonstrates CHERI memory protectionMunich, Germany, 13 March 2024 –Codasip, the leader in RISC-V Custom Compute, will demonstrate CHERI memory protection and HW/SW co-optimization at next month’s embedded world…
People to Watch 2024 – Calista RedmondCongratulations on your selection as a 2024 HPCwire Person to Watch. As a longtime electronics industry executive and the former president of the member-driven OpenPOWER…
Andes Technology: Cultivating Academic Collaboration for Over a Decade with Sustainable Spirit【Mar. 12, 2024 -Hsinchu, Taiwan】Andes Technology (TWSE: 6533), since the first agreement signed with National Chiao Tung University in 2010, has actively keeping engaged in…
What is RISC-V and Why Has it Become Important for Java?RISC stands for reduced instruction set computer, and V points to its fifth release in 2015. RISC-V is the new processor architecture to watch out for.…
Tiempo Secure announces TESIC RISC-V Secure Element IP and development kitGrenoble, France – March 8, 2023 – As security is increasingly the central issue of any SoC (System on Chip) development, for example taking into account…
Here’s Your Sneak Peek at SNUG Silicon Valley 2024Are you ready to step inside one of the premier conferences in the electronics industry? SNUG Silicon Valley 2024 will be back at the Santa…
Next Euro HPC Chip Coming Next Year Will Be in 2026 EU Exascale SystemThe next supercomputing chip for Europe’s homegrown Exascale supercomputer will come next year, according to an updated product roadmap. The 2025-bound Rhea-2 chip will succeed…
[VIDEO] RISC-V for Edge AI ApplicationsPaul Schell, Industry Analyst at ABI Research, discusses the growing start-up and legacy chipset vendor activity around RISC-V processors addressing AI workloads at the edge…
From vision to reality in RISC-V: Interview with Karel MasarikKarel Masarik is the founder of Codasip and since January 2024 also a member of the board of RISC-V International. Recently, EY named Karel Masarik the…
How the RISC-V ISA Offers Greater Design Freedom and FlexibilityThe need for more flexible and scalable processor architectures in the semiconductor industry continues to rise, contributing to the steady growth in the adoption of…
Understanding RISC-V: The Open Standard Instruction Set ArchitectureIntroduction to RISC-V RISC-V (pronounced as risk five) is an open standard Instruction Set Architecture (ISA) based on Reduced Instruction Set Computing (RISC) computer architecture.…