No recent posts listed
SiFive Announces 4th Generation of Popular Essential Product Line to Spur Innovation Across Embedded ApplicationsSemidynamics benchmarks 7bn parameter model on RISC-V AI IPAshling announces RiscFree™ C/C++ SDK support for Renesas’s RISC-V-based R9AG021 MCUsIndustry Veteran Brings Software and Hardware Experience to Role Guiding all RISC-V Technical ActivitiesRISC-V International Names Andrea Gallo as VP, Technology
Ventana CEO to Deliver a Keynote at RISC-V Summit Europe
RISC-V International Names Andrea Gallo as VP, Technology
AI, Collaboration, Security and More: Women Speak on Key Topics at RISC-V Summit International
[VIDEO] Road to testing applications on RISC-V with QEMU and Fedora – DevConf.CZ 2024
Andes Technology Showcases Leadership in AI and Automotive Applications at RISC-V Summit Europe 2024RISC-V in Brazil: Leading the Open Compute Era in Latin AmericaBreker Verification Systems Readies RISC-V CoreAssurance and SoCReady SystemVIP for Automated, Certification-level RISC-V Verification Coverage
[VIDEO] HAPS high-performance RISC-V prototyping with asynchronous clocks | Synopsys
Free tool enables customers to fully configure RISC-V cores[VIDEO] SBT C Suite Spotlight: Calista Redmond, CEO of RISC V International – Full Conversation
VeriSilicon’s industry-leading embedded GPU IP powers HPMicro’s high-performance HPM6800 series RISC-V MCUImsys develops RISC-V core, looks to AI in spaceScaleway launches its RISC-V servers in the cloud, a world first and a firm commitment to technological independence1.8 Billion Heterogenous AI Chipsets by 2030, 129 Million RISC-V AI Shipments by 2030 and 36 Other Transformative Technology Stats You Need to KnowAndes and MachineWare Collaborate on Early RISC-V Software Development for AndesCore™ AX45MPV
Tenstorrent Scores Big Design Win With Japan’s LTSC To Enable Leading-Edge 2nm AI Accelerator
[PODCAST] Leading the RISC-V Revolution, SiFive Aims to Take the Computing Industry ThroneTenstorrent RISC-V and Chiplet Technology Selected to Build the Future of AI in Japan
Ashling’s RiscFree™ SDK Toolchain now available with support for MIPS RISC-V ISA compatible P8700 and I8500 CPUs
SiFive Announces 4th Generation of Popular Essential Product Line to Spur Innovation Across Embedded ApplicationsSiFive is seeing growing adoption, with more than two billion SiFive RISC-V based chips already in the market Munich, Germany, June 25, 2024 – Today SiFive,…
Semidynamics benchmarks 7bn parameter model on RISC-V AI IPSpanish RISC-V IP developer Semidynamics has benchmarked the performance of its Tensor Unit running a LlaMA-2 7B-parameter Large Language Model (LLM) on an ‘all in…
Ashling announces RiscFree™ C/C++ SDK support for Renesas’s RISC-V-based R9AG021 MCUsJune-24 2024, RISC-V European Summit, Munich, Germany. Embedded tools developer Ashling today announced support for the Renesas R9AG021 RISC-V MCUs from Renesas in Ashling’s RiscFree…
Industry Veteran Brings Software and Hardware Experience to Role Guiding all RISC-V Technical ActivitiesMUNICH, Germany – June 24, 2024 – RISC-V International, the global open standards organization, announced that Andrea Gallo has joined as the organization’s new vice…
RISC-V International Names Andrea Gallo as VP, TechnologyIndustry Veteran Brings Software and Hardware Experience to Role Guiding all RISC-V Technical Activities MUNICH, Germany – June 24, 2024 – RISC-V International, the global open…
Ventana CEO to Deliver a Keynote at RISC-V Summit EuropeVeyron Solution — World’s Highest Performance Data RISC-V Processor and Platform — Will Be Showcased Throughout Event CUPERTINO, Calif. – June 24, 2024 – Ventana…
RISC-V International Names Andrea Gallo as VP, TechnologyIndustry Veteran Brings Software and Hardware Experience to Role Guiding all RISC-V Technical Activities MUNICH, Germany – June 24, 2024 – RISC-V International, the global…
AI, Collaboration, Security and More: Women Speak on Key Topics at RISC-V Summit InternationalIn recognition of International Women in Engineering Day on June 23, we want to shine the spotlight on some of the outstanding women in the…
[VIDEO] Road to testing applications on RISC-V with QEMU and Fedora – DevConf.CZ 2024RISC-V is an open standard instruction set architecture that has potential to be widely used as an alternative to existing ARM and x86 solutions. For…
Andes Technology Showcases Leadership in AI and Automotive Applications at RISC-V Summit Europe 2024Industry-leading RISC-V solutions and live demonstrations of CPU IP are all on display at Booth #8. Discover the latest advancements from Andes’ presentations and posters!…
RISC-V in Brazil: Leading the Open Compute Era in Latin AmericaOn June 14th, 2024, the Eldorado Research Institute in Campinas, São Paulo, hosted the RISC-V Brazil event. This gathering brought together over 200 professionals, researchers,…
Breker Verification Systems Readies RISC-V CoreAssurance and SoCReady SystemVIP for Automated, Certification-level RISC-V Verification CoverageSAN JOSE, Calif., June 20, 2024 (GLOBE NEWSWIRE) -- Breker Verification Systems, whose product portfolio solves challenges across the functional and system verification process for large,…
No recent posts listed
No recent posts listed
No recent posts listed
No recent posts listed
[VIDEO] HAPS high-performance RISC-V prototyping with asynchronous clocks | SynopsysThis video demonstrates high performance and asynchronous clocking using HAPS®-100 and HAPS ProtoCompiler software. The design uses a RISC-V Rocket System integrated highspeed DDR 4,…
Free tool enables customers to fully configure RISC-V coresSemidynamics has released its new tool called ‘Configurator’ that puts the power of Semidynamics’ full customisation of a RISC-V processor core in the hands of…
[VIDEO] SBT C Suite Spotlight: Calista Redmond, CEO of RISC V International – Full ConversationIn this installment of SBT's C-Suite Spotlight, President Justin Kinsey has a conversation with CEO of RISC-V International, Calista Redmond. Calista's early career was focused…
VeriSilicon’s industry-leading embedded GPU IP powers HPMicro’s high-performance HPM6800 series RISC-V MCUSHANGHAI--(BUSINESS WIRE)--VeriSilicon (688521.SH) today announced that HPMicro’s HPM6800 series, a new generation digital dashboard display and human-machine interface system application platform has adopted VeriSilicon’s high-performance…
Imsys develops RISC-V core, looks to AI in spaceImsys in Sweden has developed a RISC-V processor core and is part of a project to develop an AI accelerator in space. Imsys points to…
Scaleway launches its RISC-V servers in the cloud, a world first and a firm commitment to technological independenceParis, France - Thursday, February 29, 2024 - Scaleway, the European cloud provider, is proud to launch a range of RISC-V servers, marking once again its…
1.8 Billion Heterogenous AI Chipsets by 2030, 129 Million RISC-V AI Shipments by 2030 and 36 Other Transformative Technology Stats You Need to KnowThe technology community – both innovators and implementers – is at a critical juncture in 2024. Global market pressures are starting to ease, but persistent…
Andes and MachineWare Collaborate on Early RISC-V Software Development for AndesCore™ AX45MPVAachen, Germany and Hsinchu, Taiwan, February 27th 2024 MachineWare GmbH and Andes Technology (TWSE:6533), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding…
Tenstorrent Scores Big Design Win With Japan’s LTSC To Enable Leading-Edge 2nm AI AcceleratorJapan’s Leading-edge Semiconductor Technology Center, or LSTC, was established in late 2022 and is tasked with advancing the country’s research and innovation in areas such…
[PODCAST] Leading the RISC-V Revolution, SiFive Aims to Take the Computing Industry ThroneSiFive is helping lead the RISC-V revolution in automotive, Android, and AI. Senior VP Jack Kang joins the Moore’s Lobby podcast to provide his insights…
Tenstorrent RISC-V and Chiplet Technology Selected to Build the Future of AI in JapanSANTA CLARA, Calif., Feb. 27, 2024 /PRNewswire/ -- Tenstorrent is pleased to announce a multi-tiered partnership deal with Japan's Leading-edge Semiconductor Technology Center (LSTC), which selected Tenstorrent's world-class RISC-V…
Ashling’s RiscFree™ SDK Toolchain now available with support for MIPS RISC-V ISA compatible P8700 and I8500 CPUsFeb 23, 2023 SILICON VALLEY, CA, USA. Ashling and MIPS announced today that Ashling’s RiscFree SDK is now available with full support for MIPS RISC-V…