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Axiomise Heads to RISC-V Summit Europe June 25-27 in Munich
Codasip introduces best-in-class RISC-V core for power-efficient applications
[VIDEO] ANDES RISC-V CON Silicon Valley 2024
Arteris Selected by Esperanto Technologies to Integrate RISC-V Processors for High-Performance AI and Machine Learning Solutions[VIDEO] Progress in Standardizing Cryptography Extensions for RISC-V ProcessorsFirst 32-bit low-power MCU with in-house RISC-V CPU core
RISC-V International Newsletter – June 2024
HPC on RISC-V a hot topic at the International Supercomputing Conference, HamburgSpacemiT Muse Pi is a single-board PC with SpacemiT M1 8-core RISC-V processor
My Top 10 Reasons to Attend RISC-V Summit EuropeAndes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose Hotel
Designing with RISC-V Using ChipInventor
Banana Pi BPI-F3 is a single-board PC with an 8-core RISC-V processor, dual Ethernet and PCIe 2.1
Klepsydra AI and Frontgrade Gaisler Collaborate to Expand Microprocessing Versatility in Space Missions Through AI
Ashling announces Ashling’s RiscFree™ C/C++ SDK support for Codasip’s RISC-V-based L31 Core
Codasip achieves certification for automotive functional safety and cybersecurity
RISC-V Based Architecture Integrates Complex Memory Tasks to ProcessorBellSoft releases Liberica JDK 21 for RISC-V with supportRISC-V Open-Source Architecture Redefining The Future Of Computing
EDACafe Industry Predictions for 2024 – RISC-VDutch startup Innatera unveils T1: a game-changing RISC-V neural-type MCU in the edge AI sensor marketRISC-V Open-Source Architecture Redefining The Future Of ComputingEDA Back On Investors’ RadarRISC-V With Linux 6.8 Restores XIP Kernel Support
Axiomise Heads to RISC-V Summit Europe June 25-27 in MunichLONDON, June 13, 2024 (GLOBE NEWSWIRE) -- Axiomise, a company noted for enabling formal verification adoption, is headed to the RISC-V Summit Europe to demonstrate…
Codasip introduces best-in-class RISC-V core for power-efficient applicationsMunich, Germany, June 4, 2024 – Codasip, the leader in RISC-V Custom Compute, has introduced a new low-power embedded processor core, and the next generation…
[VIDEO] ANDES RISC-V CON Silicon Valley 2024ANDES had their RISC-V Con in Silicon Valley on June 11th. No worries if you weren't able to make it, watch the full conference to…
Arteris Selected by Esperanto Technologies to Integrate RISC-V Processors for High-Performance AI and Machine Learning SolutionsCAMPBELL, Calif. – June 11, 2024 – Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced that…
[VIDEO] Progress in Standardizing Cryptography Extensions for RISC-V ProcessorsThis panel will discuss the state of standardized cryptographic instruction set extensions for RISC-V processors. Lightweight instructions for scalar CPUs, high-performance instructions for vector CPUs,…
First 32-bit low-power MCU with in-house RISC-V CPU coreMouser now stocks the R9A02G021 low-power MCUs from Renesas Electronics. Empowering engineers with a multipurpose platform for creating power-efficient, cost-effective applications using an open-source ISA,…
RISC-V International Newsletter – June 2024Message from RISC-V International Events are key to the success of RISC-V, where we come together to share the latest developments and build the relationships…
HPC on RISC-V a hot topic at the International Supercomputing Conference, HamburgBy Nick Brown, Senior Research Fellow at EPCC, University of Edinburgh May the 13th saw the commencement of the 39th International Supercomputing Conference (ISC)…
SpacemiT Muse Pi is a single-board PC with SpacemiT M1 8-core RISC-V processorEarlier this year Chinese chip maker SpacemiT announced plans to launch several new products powered by the company’s RISC-V processors, including the SpacemiT Muse Book…
My Top 10 Reasons to Attend RISC-V Summit EuropeBy Tiffany Sparks, Vice President, Marketing, RISC-V International Like so many others, I am looking forward to summer travel, and I am certainly excited…
Andes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose HotelSan Jose, CA — Jun 6, 2024 — Andes Technology (TWSE: 6533), the leading vendor in high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding…
Designing with RISC-V Using ChipInventorSunnyvale, June 6th, 2024 Revolutionizing Chip Design with RISC-V ChipInventor has successfully been used to design and tape out RISC-V cores, transforming ideas into FPGA…
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Banana Pi BPI-F3 is a single-board PC with an 8-core RISC-V processor, dual Ethernet and PCIe 2.1Most of Banana Pi’s single-board computers are powered by ARM-based processors. But the upcoming Banana Pi BPI-F3 has a RISC-V processor instead. The company says the SpacemiT RISC-V K1…
Klepsydra AI and Frontgrade Gaisler Collaborate to Expand Microprocessing Versatility in Space Missions Through AIZurich, 17 January 2024 – Klepsydra AI, a leading provider of artificial intelligence (AI) software solutions, and Frontgrade Gaisler, a world leader in embedded computer systems…
Ashling announces Ashling’s RiscFree™ C/C++ SDK support for Codasip’s RISC-V-based L31 CoreJanuary-30, 2024, Limerick, Ireland. Embedded tools developer Ashling today announced support for the L31 low-power RISC-V processor core from Codasip in Ashling’s RiscFree software development…
Codasip achieves certification for automotive functional safety and cybersecurityMunich, Germany, 1 February 2024 – Codasip®, the leader in RISC-V Custom Compute, announced today that it has achieved certification for the functional safety standard…
RISC-V Based Architecture Integrates Complex Memory Tasks to ProcessorProcessor Akurra, modifies the standard RISC-V architecture and instruction set to support their memory allocation technology. VyperCore, a UK-based startup located in Bristol, has achieved…
BellSoft releases Liberica JDK 21 for RISC-V with supportSAN JOSE, Calif., Jan. 30, 2024 /PRNewswire/ -- RISC-V is a free, open RISC instruction set architecture (ISA) that is currently gaining popularity due to its high performance, flexibility,…
RISC-V Open-Source Architecture Redefining The Future Of ComputingRISC-V is revolutionising edge computing and fundamentally reshaping the broader computing landscape by promoting innovation, collaboration, and democratisation. RISC-V, an open-source instruction set architecture (ISA),…
EDACafe Industry Predictions for 2024 – RISC-VBy Mark Himelstein , CTO, RISC-V International Mark Himelstein What are the top five trends for the RISC-V open standard ISA in 2024? This year…
Dutch startup Innatera unveils T1: a game-changing RISC-V neural-type MCU in the edge AI sensor marketDutch chip startup Innatera has launched the Spiking Neural Processor T1 to target the edge AI sensor market. Read the full article.
RISC-V Open-Source Architecture Redefining The Future Of ComputingRISC-V is revolutionising edge computing and fundamentally reshaping the broader computing landscape by promoting innovation, collaboration, and democratisation. RISC-V, an open-source instruction set architecture (ISA),…
EDA Back On Investors’ RadarEDA is transforming from a staid but strategic sector into a hot investment market, fueled by strong earnings and growth, a clamoring for leading-edge and…
RISC-V With Linux 6.8 Restores XIP Kernel SupportWith Linus Torvalds back to work, merged to mainline on Wednesday were the RISC-V architecture updates for the in-development Linux 6.8 kernel cycle. One of the features for…