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Rain AI Unveils Andes Technology as Its RISC-V Partner
2024 RISC-V中国峰会赞助方案公布，赞助预定渠道6月8日全球统一开启2024 RISC-V 中国峰会演讲征集（CFP）
Andes Technology announces new SoC and development boardSeeking Sponsors for RISC-V Day Tokyo 2024!
Andes Technology Announced the QiLai SoC and the Voyager Development BoardBuilding a DIY 256-Core RISC-V computer[VIDEO] The Magic of RISC-V Vector ProcessingExciting Announcements: Unveiling the Agenda for the 2024 RT-Thread Global Tech Conference!UNVEILING THE TASKING RISC-V COMPILER | A Breakthrough regarding the development of FuSa and Cybersecurity compliant Software.World’s first RISC-V multi-mode LTE chipset for 450MHzCanonical releases Ubuntu 24.04 Server image for Milk-V Mars RISC-V SBC
StarFive RISC-V SoC’s Camera Subsystem Driver Added To Linux 6.8
VyperCore shows RTL simulation of RISC-V core, plans hardwareDebugging complex RISC-V processorsCOMPUTE THE MANDELBROT SET WITH A CUSTOM RISC-V CPU
YorChip, Inc. announces its first Chiplet for Edge AI applications with IP licensed from Semidynamics, the leader in RISC-V IP based in Barcelona
Video: Leveraging the RISC-V efficient trace (E-Trace) standardONiO looks to kill the IoT battery with RISC-V microcontrollerWhat is RISC-V and why is it important?CES: MIPS CEO Sameer Wasson sees RISC-V as path to freedomSEGGER’s new Embedded Studio: One IDE for both Arm and RISC-VDFRobot Brings RISC-V and Matter Compatibility to Its FireBeetle 2 Board with New ESP32-C6 Variant
Rain AI Unveils Andes Technology as Its RISC-V PartnerSan Francisco, CA , June 03, 2024 (GLOBE NEWSWIRE) -- Rain AI Licenses Andes AX45MPV and Taps Andes Custom Computing BU to Accelerate Its Launch…
2024 RISC-V中国峰会赞助方案公布，赞助预定渠道6月8日全球统一开启2024 RISC-V中国峰会的赞助方案现已公开，欢迎下载阅览和邮件垂询。 您可以通过点击阅读原文跳转至官网链接，也可以在CNRV公众号聊天窗口输入【峰会赞助】获得赞助资料的下载链接地址。 Download Sponsorship Slides (If you live in mainland China and have issues when trying to download the file from GitHub, try this link to…
2024 RISC-V 中国峰会演讲征集（CFP）第4届 RISC-V 中国峰会（RVSC2024）定于8月19至25日举办，其中主会和展会于21-23日在浙江杭州黄龙饭店举行。经过几年的发展，RISC-V中国峰会已经成为全球三大RISC-V专业会展之一、国内最大的RISC-V年度活动。今年预计将会吸引超过三千名国内外观众线下参与、超过五十万观众线上观看，同时预计会有超过一百家企业及研究机构、开源技术社区参会。本次峰会也是2021年创办以来首次在浙江杭州举办，欢迎全球RISC-V生态伙伴及企业莅临。 RISC-V国际基金会是全球RISC-V峰会的领导者。2024 RISC-V中国峰会组织委员会（组委会）负责中国峰会具体的筹备和协调。程序委员会负责对演讲申请的评审。组委会认真听取总结往届峰会后观众的反馈意见和建议，今年峰会拟设置更多的演讲分会场、分论坛，提供更多的演讲机会和更长的演讲时长，满足参会演讲者的交流分享需求。欢迎所有从事RISC-V相关研发及产业的伙伴踊跃投稿。 重要日期 提交开始日期：2024 年 5 月 28 日 提交截止日期：2024年 6 月 22 日（AoE） 作者录用通知：2024 年 7 月 7 日 初步议程公告：2024 年 7 月 18 日 幻灯片定稿：2024 年 8 月 8 日 峰会召开时间：2024年 8 月 19 日至 25 日 投稿说明 我们邀请提交与 RISC-V 相关的演讲，讨论以下感兴趣的技术主题： RISC-V + AI 相关的IP/SoC/Chip设计、解决方案、AI软件栈、指令集标准化方面的最新工作进展 汽车、消费电子等领域的应用案例…
Andes Technology announces new SoC and development boardAndes Technology, a supplier of 32/64-bit RISC-V processor cores, has unveiled the QiLai SoC and the Voyager development board to help accelerate the development and…
Seeking Sponsors for RISC-V Day Tokyo 2024!Join us at RISC-V Day Tokyo 2024 on August 1 at the University of Tokyo's Ito International Academic Research Center. We’re looking for sponsors to…
Andes Technology Announced the QiLai SoC and the Voyager Development BoardMay 30, 2024 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding…
Building a DIY 256-Core RISC-V computerIf you’re interested in building your very own 256-Core RISC-V supercomputer, you might find this project video intriguing. It details the ambitious method of creating…
[VIDEO] The Magic of RISC-V Vector ProcessingThe 1.0 RISC-V Vector Specification is now Ratified, and the first pieces of silicon using the new spec are starting to hit the shelves. I…
Exciting Announcements: Unveiling the Agenda for the 2024 RT-Thread Global Tech Conference!RT-Thread IoT OS is thrilled to unveil the agenda for the highly anticipated 2024 RT-Thread Global Tech Conference (RGTC). This year’s event promises to be…
UNVEILING THE TASKING RISC-V COMPILER | A Breakthrough regarding the development of FuSa and Cybersecurity compliant Software.Author: Gerard Vink INTRODUCTION TASKING, a leading provider of innovative compiler solutions for the automotive functional safety sector, has introduced a compiler toolset for the…
World’s first RISC-V multi-mode LTE chipset for 450MHzGCT Semiconductor has developed the first multi-mode LTE chipset for the 450MHz spectrum, using two RISC-V cores. The GDM7243SL developed by GCT is the world’s…
Canonical releases Ubuntu 24.04 Server image for Milk-V Mars RISC-V SBCCanonical has been releasing Ubuntu RISC-V images for SBCs and QEMU at least since 2021. The latest addition is an Ubuntu 24.04 Server image for…
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StarFive RISC-V SoC’s Camera Subsystem Driver Added To Linux 6.8Sent in last week were all of the media driver updates for Linux 6.8. Arguably most notable is the introduction of the StarFive Camera Subsystem…
VyperCore shows RTL simulation of RISC-V core, plans hardwareVyperCore in the UK has passed a major development milestone in the development of a new chip architecture starting with RISC-V. Bristol-based VyperCore is developing…
Debugging complex RISC-V processorsRISC-V processors are quickly becoming mainstream. The open standard means freedom for many developers, but success depends on the development of a support ecosystem around…
COMPUTE THE MANDELBROT SET WITH A CUSTOM RISC-V CPUWhen faced with an FPGA, some people might use it to visualize the Mandelbrot set. Others might use it to make CPUs. But what happens…
YorChip, Inc. announces its first Chiplet for Edge AI applications with IP licensed from Semidynamics, the leader in RISC-V IP based in BarcelonaSAN RAMON, CA, 94582 -- January 17, 2024 -- YorChip, Inc. announces its first Chiplet for Edge AI applications with IP licensed from Semidynamics, the leader…
Video: Leveraging the RISC-V efficient trace (E-Trace) standardUnderstanding program behavior in complex systems is not easy. Understanding the behavior of complete systems is even more challenging. Get non-intrusive, full-speed and system-level visibility…
ONiO looks to kill the IoT battery with RISC-V microcontrollerA Norwegian chip startup is aiming to eliminate the need for batteries in trillions of devices across the Internet of Things (IoT) Kjetil Meisal, CEO…
What is RISC-V and why is it important?RISC-V, an open-source instruction set architecture (ISA), has been making waves in the world of computer architecture. “RISC-V” stands for Reduced Instruction Set Computing (RISC)…
CES: MIPS CEO Sameer Wasson sees RISC-V as path to freedomSameer Wasson is passionate about RISC-V architecture and recently became CEO of MIPS to show the world how important an architecture it is. He uses…
SEGGER’s new Embedded Studio: One IDE for both Arm and RISC-VSEGGER is excited to announce the new Embedded Studio - V8.10. This cutting-edge, multi-platform IDE now also supports multiple architectures with a single setup. The same software…
DFRobot Brings RISC-V and Matter Compatibility to Its FireBeetle 2 Board with New ESP32-C6 VariantDFRobot has launched a new FireBeetle 2, swapping out the original design's Espressif ESP32-S3 chip for the RISC-V-based ESP32-C6 — which brings with it support…