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Tenstorrent and MosChip Partner on High Performant RISC-V Design
embedded world 2024: Codasip demonstrates CHERI memory protection
People to Watch 2024 – Calista RedmondAndes Technology: Cultivating Academic Collaboration for Over a Decade with Sustainable SpiritWhat is RISC-V and Why Has it Become Important for Java?
Adding Physical Memory Protection to the VeeR EL2 RISC-V CoreTiempo Secure announces TESIC RISC-V Secure Element IP and development kit
Here’s Your Sneak Peek at SNUG Silicon Valley 2024
Spotlighting Women in the Global RISC-V Community this International Women’s DayNext Euro HPC Chip Coming Next Year Will Be in 2026 EU Exascale System[VIDEO] RISC-V for Edge AI ApplicationsFrom vision to reality in RISC-V: Interview with Karel Masarik
Codasip announces next-generation RISC-V processor family for Custom ComputeResearch Consortium sets Standards in the Field of Open Source Hardware: Open Tools used for a Security ChipWhat is RISC-V and how will it redefine your next-gen wearable tech?
Andes Technology Unveils Andes D23 and N225 Cores Pioneering the Next Generation of Compact, Performant, and Secure RISC-V Processor Technology
Qualcomm to Bring RISC-V Based Wearable Platform to Wear OS by GoogleQualcomm Adopts RISC-V for Next-Gen Snapdragon Wear PlatformSharpRISCV Overview: A Browser-Based RISC-V Assembler for Seamless Learning and Exploration
Codasip announces next-generation RISC-V processor family for Custom ComputeCodasip 700 RISC-V processor family: Bringing the world of Custom Compute to everyone
SiFive Rolls Out RISC-V Cores Aimed at Generative AI and MLSiFive unveils two new high-performance RISC-V processorsSiFive Announces Differentiated Solutions for Generative AI and ML Applications Leading RISC-V into a New Era of High-Performance Innovation
Tenstorrent and MosChip Partner on High Performant RISC-V DesignSANTA CLARA, Calif., March 13, 2024 /PRNewswire/ --Tenstorrent and MosChip Technologies announced today that they are partnering on design for Tenstorrent's cutting-edge RISC-V solutions. In selecting MosChip…
embedded world 2024: Codasip demonstrates CHERI memory protectionMunich, Germany, 13 March 2024 –Codasip, the leader in RISC-V Custom Compute, will demonstrate CHERI memory protection and HW/SW co-optimization at next month’s embedded world…
People to Watch 2024 – Calista RedmondCongratulations on your selection as a 2024 HPCwire Person to Watch. As a longtime electronics industry executive and the former president of the member-driven OpenPOWER…
Andes Technology: Cultivating Academic Collaboration for Over a Decade with Sustainable Spirit【Mar. 12, 2024 -Hsinchu, Taiwan】Andes Technology (TWSE: 6533), since the first agreement signed with National Chiao Tung University in 2010, has actively keeping engaged in…
What is RISC-V and Why Has it Become Important for Java?RISC stands for reduced instruction set computer, and V points to its fifth release in 2015. RISC-V is the new processor architecture to watch out for.…
Adding Physical Memory Protection to the VeeR EL2 RISC-V CoreAntmicro’s work with CHIPS Alliance’s Caliptra Root of Trust project, led by Google, AMD, NVIDIA, and Microsoft focuses around providing automated testing and verification infrastructure…
Tiempo Secure announces TESIC RISC-V Secure Element IP and development kitGrenoble, France – March 8, 2023 – As security is increasingly the central issue of any SoC (System on Chip) development, for example taking into account…
Here’s Your Sneak Peek at SNUG Silicon Valley 2024Are you ready to step inside one of the premier conferences in the electronics industry? SNUG Silicon Valley 2024 will be back at the Santa…
Spotlighting Women in the Global RISC-V Community this International Women’s DayInternational Women's Day, celebrated annually on March 8, recognizes the remarkable achievements of women across the globe. It is an important day to acknowledge the…
Next Euro HPC Chip Coming Next Year Will Be in 2026 EU Exascale SystemThe next supercomputing chip for Europe’s homegrown Exascale supercomputer will come next year, according to an updated product roadmap. The 2025-bound Rhea-2 chip will succeed…
[VIDEO] RISC-V for Edge AI ApplicationsPaul Schell, Industry Analyst at ABI Research, discusses the growing start-up and legacy chipset vendor activity around RISC-V processors addressing AI workloads at the edge…
From vision to reality in RISC-V: Interview with Karel MasarikKarel Masarik is the founder of Codasip and since January 2024 also a member of the board of RISC-V International. Recently, EY named Karel Masarik the…
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Codasip announces next-generation RISC-V processor family for Custom ComputeIntroducing the highly flexible 700 family for unlimited innovation Munich, Germany, 17 October 2023 – Codasip, the leader in RISC-V Custom Compute, announced today a…
Research Consortium sets Standards in the Field of Open Source Hardware: Open Tools used for a Security ChipThe security chip (at the middle of the bottom) is built in flip-chip technology on an auxiliary board and plugged into a standard socket on…
What is RISC-V and how will it redefine your next-gen wearable tech?When discussing computer hardware, x86, and ARM are household names when discussing microprocessor architecture. They've been around for decades and are still going strong, powering…
Andes Technology Unveils Andes D23 and N225 Cores Pioneering the Next Generation of Compact, Performant, and Secure RISC-V Processor TechnologyHsinchu, Taiwan – Oct. 17, 2023 – Andes Technology, the renowned supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V…
Qualcomm to Bring RISC-V Based Wearable Platform to Wear OS by GoogleHighlights: Qualcomm and Google are extending their collaboration on wearables by developing a RISC-V Snapdragon Wear™ platform that will power next-generation Wear OS solutions. Work…
Qualcomm Adopts RISC-V for Next-Gen Snapdragon Wear PlatformQualcomm and Google announced that they had agreed to expand their partnership to development of a Snapdragon Wear platform based on the RISC-V instruction set…
SharpRISCV Overview: A Browser-Based RISC-V Assembler for Seamless Learning and ExplorationIn the ever-evolving landscape of computer architecture, RISC-V stands out as an open-source instruction set architecture that offers flexibility and adaptability. To facilitate learning and…
Codasip announces next-generation RISC-V processor family for Custom ComputeMunich, Germany -- October 17, 2023 – Codasip®, the leader in RISC-V Custom Compute, announced today a new highly configurable family of RISC-V baseline processors for…
Codasip 700 RISC-V processor family: Bringing the world of Custom Compute to everyoneToday, technology innovators must have new ways to create differentiated products. How are they supposed to meet the demand for more computational performance when semiconductor scaling…
SiFive Rolls Out RISC-V Cores Aimed at Generative AI and MLSiFive has released two new processors, one to target machine learning applications, and one to target general-purpose HPC. The RISC-V movement is one of the…
SiFive unveils two new high-performance RISC-V processorsSiFive, a RISC-V processor design firm, unveiled two new chip designs aimed at bringing a high-performance computing solution to various industries. The announcement of the…
SiFive Announces Differentiated Solutions for Generative AI and ML Applications Leading RISC-V into a New Era of High-Performance InnovationSanta Clara, Calif., Oct. 11, 2023 –SiFive, Inc., the pioneer and leader of RISC-V computing today announced two new products designed to address new requirements for…