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Andes Announces General Availability of the New RISC-V Out-Of-Order Superscalar Multicore Processor, the AndesCore™ AX65

Hsinchu, Taiwan, Jan. 04, 2024 (GLOBE NEWSWIRE) -- Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member…

WCH RISC-V microcontrollers can now be programmed with the Arduino IDE

WCH has launched some interesting RISC-V microcontrollers in the last year or so, including the “10 cents” CH32V003 RISC-V microcontroller with 2KB SRAM and 16KB flash or…

Expanding RISC-V support in Renode with Bit-Manipulation extensions

Antmicro’s open source Renode simulation framework offers support for various instruction set architectures, with the RISC-V ISA being a major focus for – as a…

Five Leading Semiconductor Industry Players Incorporate New Company, Quintauris, to Drive RISC-V Ecosystem Forward

MUNICH--(BUSINESS WIRE)--Semiconductor industry players Robert Bosch GmbH, Infineon Technologies AG, Nordic Semiconductor ASA, NXP® Semiconductors, and Qualcomm Technologies, Inc., have formally established Quintauris GmbH. Headquartered…

Adding Physical Memory Protection to the VeeR EL2 RISC-V Core

Antmicro’s work with CHIPS Alliance’s Caliptra Root of Trust project, led by Google, AMD, NVIDIA, and Microsoft focuses around providing automated testing and verification infrastructure including code quality…

[VIDEO] Synopsys ARC-V RISC-V Processor IP | Synopsys

Synopsys ARC-V Processor IP delivers the optimal power-performance-efficiency and extensibility of ARC processors with broad software and tools support from Synopsys and the expanding RISC-V…

RISC-V 双周报第72期:OpenAI自研RISC-V架构芯片,国内各项竞赛频现RV赛道(20231215)

完整的双周报信息可以点击这里查看。感谢芯来科技整理和发布。 以下是部分摘录: 「50万奖金!面向RISC-V架构的AI开发框架构建与优化大赛等你来战!」 「芯来科技:芯来RISC-V车规级CPU IP助力汽车电子市场“芯”应用」 「PLCT实验室2023开放日议程公布」 「第15届开源开发工具大会(OSDT2023)演讲征集」 「RISC-V喜提FFmpeg官方社区推广,PLCT实验室新人员工孙越池助力FFmpeg性能提升」

RISC-V hardware ecosystem gets strong industry support – Qualcomm joins with four other industry players to form Quintauris

Qualcomm and four other significant semiconductor firms have officially joined forces to establish Quintauris, a company focused on developing "next-generation hardware" based on the RISC-V…

RISC-V International Newsletter – December 2023

Message from RISC-V International As we look back on 2023, we wanted to express our gratitude to the entire RISC-V ecosystem. Throughout the year, we…

World’s first RISC-V handheld gaming system announced — retro gaming platform uses Linux

RISC-V-based processors have been making inroads into a wide range of applications, from tiny microcontrollers to data center processors. However, RISC-V hasn't been used for many…

RISC-V is Creating a ‘Linux Movement’ in Hardware

In 1991, when Linus Torvalds created Linux, an open-source operating system, it threatened Microsoft’s business as Linux was an alternative to one of its core…

RISC-V Summit report: Meta leads the way for custom processors

As a regular attendee of the RISC-V Summit US, I’ve come to appreciate the unique blend of cutting-edge technology discussions and the sunny California weather.…

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Semidynamics Released its 4-way Atrevido 423 RISC-V Core

Barcelona, Spain. Semidynamics released its 64-bit flexible 4-way Atrevido 423 RISC-V core delivering double the instructions than the 2-way, 223 core. More functioning units are utilized…

Semidynamics Released its 4-way Atrevido 423 RISC-V Core

Barcelona, Spain. Semidynamics released its 64-bit flexible 4-way Atrevido 423 RISC-V core delivering double the instructions than the 2-way, 223 core. More functioning units are utilized…

AMD Readies “New Stuff” For Linux 6.6 Graphics Driver, AMDGPU DC For RISC-V

Sent out today was a batch of "new stuff" for the AMDGPU and AMDKFD kernel graphics drivers for queuing in DRM-Next ahead of the Linux…

RISC-V Finds Its Foothold in a Rapidly Evolving Processor Ecosystem

Developers have grown up hearing ARM or x86 being the guts of PCs and servers, but an alternative architecture called RISC-V is emerging. In the next few…

Re-Targetable LLVM C/C++ Compiler For RISC-V

RISC-V is a modular instruction set architecture (ISA) with great customization capabilities that enable innovation and differentiation without fragmentation. On top of the baseline modules…

Re-Targetable LLVM C/C++ Compiler For RISC-V

RISC-V is a modular instruction set architecture (ISA) with great customization capabilities that enable innovation and differentiation without fragmentation. On top of the baseline modules…

Semidynamics announces fully customisable, 4-way Atrevido 423 RISC-V core for big data applications

Barcelona, Spain – 20 July, 2023. Semidynamics, the only provider of fully customisable RISC-V processor IP, has launched the next member of its Atrevido family…

Vitra-XS Debug & Trace Probe

Vitra-XS is Ashling’s Debug & Trace Probe for embedded development with support for multiple target architectures including RISC-V, Arm and Synopsys ARC powered systems. Vitra-XS works with Ashling’s RiscFree™…

Debian GNU/Linux Is Now Officially Supported on the RISC-V Architecture

The Debian Project announced today that the RISC-V (riscv64) hardware architecture is now officially supported by the Debian GNU/Linux operating system. Until today, Debian was officially supported…

Leveraging RISC-V architecture to boost economic development

The revolution in computing is unfolding in an unlikely place – not just in the world’s Silicon Valley but potentially in third-world countries. The harbinger…

Ashling announce RiscFree™ support for MachineWare’s SIM-V RISC-V Instruction Set Simulator.

Limerick, Ireland. 29th May 2023 - Ashling announced today that Ashling’s RiscFree SDK now provides target debug support for MachineWare’s SIM-V RISC-V Instruction Set Simulator.…

Semidynamics announces fully customisable, 4-way, Atrevido 423 RISC-V core

The Atrevido 423 has a wider, 4-way pipeline, allowing for the decoding and retirement of up to two times more instructions than its recently launched,…