[PODCAST] A Tour of the RISC-V Movement and SiFive’s Contributions with Jack KangDan is joined by Jack Kang of SiFive. As a member of the founding team at SiFive, Jack oversees the Business Development, Customer Experience, and Corporate…
[VIDEO] The RISC-V RevolutionRISC-V is a fast growing CPU architecture. This talk will give you an overview on what is driving the RISC-V eco-system. We will look into…
RISC-V Summit 2023: RISC-V is Here for Developers!RISC-V Summit North America 2023 brought the RISC-V ecosystem together to share the latest technology solutions, proving that #riscvishere! A key takeaway from the show…
Renesas has announced one of the first independently developed 32-bit RISC-V CPUs. Renesas, long a major player in the industrial MCU and CPU universe, has…
[VIDEO] RISC-V Summit 2023 – Recap from OpenHW GroupCheck out our video recap to see how we plan on keeping the momentum going. We look forward to bringing you exciting updates, collaborations, and…
One of the largest vendors of embedded processors has independently developed a CPU core for the 32-bit general-purpose RISC-V market; it can be used as…
RISC-V Summit Buzz – Semidynamics Founder and CEO Roger Espasa Introduces Extreme CustomizationFounded in 2016 and based in Barcelona, Spain, Semidynamics™ is the only provider of fully customizable RISC-V processor IP. The company delivers high bandwidth, high…
RISC-V to the Core: New HorizonsThe increasing popularity of the RISC-V ISA within the semiconductor industry is a boon for innovation. It provides designers with unprecedented flexibility and will slowly…
Canonical joins the RISC-V Software Ecosystem (RISE)Canonical is delighted to announce it is now a member of the RISC-V Software Ecosystem (RISE) to contribute to commercial readiness of open source software for…
RISC-V Summit Buzz – Axiomise Accelerates RISC-V Designs with Next Generation formalISA®If the recent RISC-V Summit proved one thing it’s that open-source hardware design, and particularly the RISC-V instruction set architecture (ISA) has entered the mainstream.…
Many have waited years to hear someone like Prahlad Venkatapuram, Senior Director of Engineering at Meta, say what came out this week at the RISC-V…
DAC 2023: RISC-V is not in the future, it’s nowAt this year’s Design Automation Conference (DAC), there was a panel discussion entitled, “Delivering on RISC V’s Promise to Give Designers Freedom to Innovate –…
Dan is joined by Calista Redmond, CEO of RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including Vice President of IBM Z…
VIDEO: DAC 2023, Day 3: ‘CHIPS Acts,’ RISC-V, More AIIn this video report, EE Times reporters Sally Ward-Foxton and Nitin Dahad discuss what they saw and heard at the third day of the Design Automation…
AnalogLamb Announces RISC-V Polos Development Boards, Starting at Just $1.99Beijing-based embedded hardware specialist AnalogLamb has announced three new low-cost entries in its Polos family of development boards, all powered by RISC-V microcontrollers from WCH…
Farnell is now stocking the newly introduced BeagleV®-Ahead, the first professional, open-source mass production RISC-V single board computer (SBC) by Beagleboard.org®. BeagleV®-Ahead is in the…
BeagleBoard.org is now delivery its BeagleV-Ahead single board computer (SBC) based on the TH1520, a quad core 64-bit RISC-V SoC from T-Head. The SBC utilizes the open-source…
BeagleBoard has launched a new single-board computer called the BeagleV-Ahead. It’s the same shape as the company’s BeagleBone Black and it’s compatible with some accessories designed for that…
BeagleBoard.org®, a leading developer of open-source hardware platforms, is thrilled to announce the highly anticipated launch of BeagleV® Ahead, an innovative single board computer (SBC) based…
Bluespec’s newest RISC-V chip adds customization capabilities for edge workloadsBluespec, a RISC-V tools and silicon IP provider, has introduced a processor design based on the open standard RISC-V instruction set architecture that will allow…
A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs Lukas Gerlach (CISPA Helmholtz Center for Information Security), Daniel Weber (CISPA Helmholtz Center for Information Security),…
Abstract—The complexity of automotive systems is increasing quickly due to the integration of novel functionalities such as assisted or autonomous driving. However, increasing complexity poses…
Imperas Software in the UK and Cadence Design Systems have detailed the verificaiton flow for NSITEXE developing an automotive AI RISC-V processor core. The two…