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[VIDEO] RISC-V Taipei Day: Trends In Ai & Automotive

The AI & automotive industry are both undergoing a major transformation. AI is being used to improve safety, efficiency, and comfort in vehicles, and it…

[VIDEO] 023 RISC-V Taipei Day: Extending RISC-V Intelligence From Cloud To Edge

Equipped with RISC-V's powerful Vector ISA and automated customer extension framework, Andes solutions have been adopted in over a dozen innovated datacenter AI/ML accelerators such…

[VIDEO] 2023 RISC-V Taipei Day: Scalable RISC-V For Digital Transformation

The human race is entering an era in which digital technology is profoundly transforming every aspect of human life. Digital transformation refers to the use…

[VIDEO] 2023 RISC-V Taipei Day: Bridging The Divide – Unifying RISC-V Through Binary Translation

In the ever-evolving landscape of RISC-V ISA, binary translation emerges as a critical enabler for its continuous evolution and innovation, effectively managing the potential fragmentation…

[VIDEO] 2023 RISC-V Taipei Day: RISC-V is Leading Technology in the World

RISC-V has stood on par with x86 and ARM, establishing itself as one of the three leading global instruction sets for the coming several decades,…

2023 RISC-V Taipei Day: RISC-V is Inevitable

RISC-V adoption has accelerated across domains, from embedded to enterprise, from automotive to HPC. RISC-V has grown faster than any other architecture in history with…

Andes Technology Partners with WITTENSTEIN high integrity systems (WHIS) to Build Safety-Critical Solutions with RISC-V Processors

Hsinchu, Taiwan, Nov. 13, 2023 (GLOBE NEWSWIRE) -- Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and…

Understanding RISC-V: The Open Standard Instruction Set Architecture

With a groundbreaking open-source architecture, RISC-V is paving the way for a new era of computing technology. In this article, we’ll delve into RISC-V’s evolution,…

Integrating PikeOS With Microchip’s RISC-V Based PolarFire® SoC FPGA

This blog post reviews the RTOS developed by SYSGO GmbH, PikeOS, and the process for building and integrating an embedded system with PikeOS and Microchip's PolarFire® SoC…

[VIDEO] Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips

As semiconductor industry leaders, Bosch, Infineon, Nordic Semiconductor, NXP, and Qualcomm collaborate to drive the acceleration of automotive RISC-V semiconductors, join us for an insightful…

RISC-V Summit 2023: Embedded Editor Report, Day 2

In a release, Calista Redmond, CEO of RISC-V International, said, “The biggest takeaway for the RISC-V community this year is that we’re going to see…

RISC-V: Projected Growth to Over 16 Billion Chips by 2030

The RISC-V open standard instruction set architecture (ISA) has made significant strides since its introduction in August 2014. According to RISC-V International, it has already been incorporated…

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Bluespec’s MCUX RISC-V Processor Ideal for FPGAs and ASICs

Framingham, Massachusetts. Bluespec Inc. released its MCUX RISC-V processor designed to simplify the integration of customize protocols and add accelerators to FPGAs and ASICs. The platform…

VIDEO: EUPILOT: Europe’s HPC and AI pre-exascale accelerator demonstrator

The EUPILOT project aims to establish a European-based accelerator platform for high-performance computing (HPC) and AI. It seeks to achieve European digital sovereignty in HPC, promote the adoption of the RISC-V…

Tiempo Secure’s new TESIC RISC-V IP successfully passes SERMA CC EAL5+ security assessment tests

Grenoble, France – July 3, 2023 – Tiempo Secure’s latest TESIC design, a Secure Element targeting applications such as iSIM, eSE, Payment, UWB, Digital ID, IoT…

VMware join hands with Samsung, AMD, RISC-V for confidential computing

VMware recently announced at the Confidential Computing Summit 2023 that it is partnering with chipmakers Samsung, AMD, and the RISC-V Keystone community for a project to help accelerate…

Tiempo Secure’s new TESIC RISC-V IP successfully passes SERMA CC EAL5+ security assessment tests

Grenoble, France – July 3, 2023 – Tiempo Secure’s latest TESIC design, a Secure Element targeting applications such as iSIM, eSE, Payment, UWB, Digital ID, IoT…

VMware, Other Tech Giants Announce Push for Confidential Computing Standards

In conjunction with the 2023 Confidential Computing Summit last week, VMware announced a partnership with tech giants to accelerate the development of confidential computing applications.…

Customizable RISC-V processor is vendor-independent

Bluespec’s MCUX RISC-V processor allows developers to implement custom instructions and add accelerators to FPGAs and ASICs. MCUX joins the company’s MCU RISC-V family of…

Chinese Researchers Used AI to Design RISC-V CPU in Under 5 Hours

A group of Chinese scientists has published (PDF) a paper titled "Pushing the Limits of Machine Design: Automated CPU Design with AI." The paper details the researchers'…

VMware, AMD, Samsung and RISC-V push for confidential computing standards

VMware has joined AMD, Samsung, and members of the RISC-V community to work on an open and cross-platform framework for the development and operation of…

VMware partners with Samsung, AMD and RISC-V to accelerate confidential computing

VMware Inc. stepped up its efforts to accelerate the adoption of confidential computing today, announcing an alliance with chipmakers Samsung Electronics Co. Ltd. and Advanced Micro Devices Inc., as…

China Mobile releases two self-developed RISC-V communications chips

China Mobile recently released the world's first LTE-Cat.1 chip with pure self-developed RISC-V architecture, as well as its first pure self-developed mass-production cellular IoT communications…

The European Project Creating Extensible, Energy-Efficient RISC-V CPUs

Some European researchers are developing open-source RISC-V cores to compete with x86 and Arm, and are relying on only €8 million in funding. Details about…