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Ashling announce RiscFree™ C/C++ SDK support for the newly launched Synopsys ARC-V RISC-V ISA based Processors
RISC-V International Marks Banner Year for RISC-V Adoption, Technical Momentum, and Community Engagement
Accelerating the Open Source Software Ecosystem with RISC-V Labs
High performance GPU cores for cloud gaming with RISC-V
The Rise of RISC-V: From University Lab to Global Force in Silicon Design
Ubilite Licenses RISC-V Application Processor IP Core from CAST
Andes and Vector Propel RISC-V AUTOSAR Software Innovations for the Automotive Industry
What is RISC-V? CTO Mark Himelstein Explains Its Role in Computer Science – The Electropages Podcast
Tenstorrent and Imperas Set to Provide Model of RISC-V Core
Debugging RISC-V processors using E-Trace
RISC-V International Newsletter – November 2023
Imperas RISC-V solutions for developers – accelerating RISC-V
DFRobot Launches the All-In-One UNIHIKER, a Single-Board Arm Computer with Display and RISC-V MCUMilk-V Unveils Its Third RISC-V Board in a Month: The $9 Dual-Core Linux-Capable Milk-V Duo
RISC-V gathers pace in EuropeStartup plans customizable RISC-V edge AI speech processor | Nick Flaherty, EE News EuropeImagination, GHS team for RTOS and tools on RISC-V CPUs | Nick Flaherty, EENews Europe
Agile Analog launches first complete RISC-V analog IP subsystem at RISC-V Summit Europe
Interview with Calista Redmond – RISC-V summit Barcelona
Configurable 64-bit RISC-V IP Targets Machine Learning, Other Advanced Apps | Alix Paultre, Electronic DesignComputing at the Ultimate Edge – Space | Wisse Hettinga, EENews EuropeThe RISC-V Report – interviewing the key players (2017-2023)Agile Analog launches first complete RISC-V analog IP subsystemComplete RISC-V analog IP subsystem targets IoT | Jean-Pierre Joosting, EE News Europe
Ashling announce RiscFree™ C/C++ SDK support for the newly launched Synopsys ARC-V RISC-V ISA based ProcessorsNovember-7, 2023, RISC-V Summit, Santa Clara, Silicon Valley, California, USA Ashling today announced support for the Synopsys ARC-V RISC-V ISA compliant Processor family. Ashling, as…
RISC-V International Marks Banner Year for RISC-V Adoption, Technical Momentum, and Community EngagementRISC-V adoption continues to expand across key vertical markets including aerospace, AI/ML, automotive, data center, embedded, HPC, and security Santa Clara, Calif. – Nov. 7,…
Accelerating the Open Source Software Ecosystem with RISC-V LabsThe momentum that RISC-V is achieving across the compute spectrum is amazing. Throughout 2023, we have seen RISC-V based computing being applied to every kind…
High performance GPU cores for cloud gaming with RISC-VImagination Technologies in the UK has launched a line of high-performance GPU IP with support for DirectX for cloud-based streaming gaming systems The IMG DXD includes…
The Rise of RISC-V: From University Lab to Global Force in Silicon DesignRISC-V originated in academia as a summer project and later turned into a global phenomenon driving a new era of innovation in the semiconductor industry. Today,…
Ubilite Licenses RISC-V Application Processor IP Core from CASTRISC-V Summit, Santa Clara, California — November 7, 2023 -- Semiconductor intellectual property provider CAST today announced that ultra-low-power Wi-Fi chipset developer Ubilite, Inc. has licensed…
Andes and Vector Propel RISC-V AUTOSAR Software Innovations for the Automotive IndustryHsinchu, Taiwan and Stuttgart, Germany – Nov. 6, 2023 – Andes Technology, the renowned supplier of high-efficiency, low-power 32/64-bit RISC-V processors and a Founding Premier member…
What is RISC-V? CTO Mark Himelstein Explains Its Role in Computer Science – The Electropages PodcastIn this very special episode of the Electropages podcast, host Robin Mitchell gets a chance to talk with Mark Himelstein, Chief Technology Officer of RISC-V…
Tenstorrent and Imperas Set to Provide Model of RISC-V CoreIn a recent release, Imperas Software, a RISC-V simulation solutions company, announced that it has teamed up with Tenstorrent, an AI computing company, to make available…
Debugging RISC-V processors using E-TraceBy: Siemens | Tessent Embedded Analytics | Author: Huw Geddes, Product Manager Debugging RISC-V-based SoCs can be challenging even for devices with only a few…
RISC-V International Newsletter – November 2023Message from RISC-V International Greetings! We’re in the final countdown to RISC-V Summit North America, which runs Nov. 6-8 in Santa Clara, CA. The anticipation and…
Imperas RISC-V solutions for developers – accelerating RISC-VImperas Software has introduced the latest product updates as a general release to all customers and users. These product updates include the latest models of…
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DFRobot Launches the All-In-One UNIHIKER, a Single-Board Arm Computer with Display and RISC-V MCUDFRobot has announced the launch of a new all-in-one single board computer (SBC) development platform, designed for plug-and-play programming and bringing its own 2.8" touchscreen…
Milk-V Unveils Its Third RISC-V Board in a Month: The $9 Dual-Core Linux-Capable Milk-V DuoRISC-V startup Milk-V has announced yet another development board built around the free and open source instruction set, this time a compact development device clearly…
RISC-V gathers pace in EuropeThe RISC-V Summit Europe brought together developers, architects, technical decision and policy makers from across European RISC-V ecosystem for the first time in the region…
Startup plans customizable RISC-V edge AI speech processor | Nick Flaherty, EE News EuropeAONDevices has developed an efficient edge AI denoising technology for applications that require minimal power and latency running on its forthcoming accelerator IP and hardware…
Imagination, GHS team for RTOS and tools on RISC-V CPUs | Nick Flaherty, EENews EuropeGreen Hills Software has ported its µ-velOSity safety- and security-certified real-time operating system (RTOS) to the real time RISC-V cores developed by Imagination Technologies, with…
Agile Analog launches first complete RISC-V analog IP subsystem at RISC-V Summit EuropeAgile Analog, the customisable analog IP company, is launching the first complete analog IP subsystem for RISC-V applications at the RISC-V Summit Europe in Barcelona…
Interview with Calista Redmond – RISC-V summit BarcelonaAt the RISC-V summit in Barcelona eeNews is meeting up with Calista Redmond. She is the CEO of RISC-V International. In our conversation we are…
Configurable 64-bit RISC-V IP Targets Machine Learning, Other Advanced Apps | Alix Paultre, Electronic DesignConfigurable high-bandwidth RISC-V cores with vector units can be made to directly address challenging applications like machine learning, AI, and other cutting-edge spaces. Semidynamics is a…
Computing at the Ultimate Edge – Space | Wisse Hettinga, EENews EuropeeeNews Europe is meeting up with Gerard Rauwerda, Business Developer with Technolution. We discuss the RISC-V developments over the years and the role Technolution played,…
The RISC-V Report – interviewing the key players (2017-2023)Take time for the The RISC-V Summit in Barcelona and connect the dots of this Open Instruction Set Architecture In 2017 we had the opportunity…
Agile Analog launches first complete RISC-V analog IP subsystemAgile Analog has brought together its customisable IP blocks to create the first complete analog IP subsystem for battery-powered RISC-V chips. The initial subsystem includes…
Complete RISC-V analog IP subsystem targets IoT | Jean-Pierre Joosting, EE News EuropeAgile Analog is offering the first complete analog IP subsystem for RISC-V applications at the RISC-V Summit Europe in Barcelona. The initial subsystem includes all the analog…