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Ashling announce RiscFree™ support for MachineWare’s SIM-V RISC-V Instruction Set Simulator.
Semidynamics announces fully customisable, 4-way, Atrevido 423 RISC-V core
RiscFree C/C++ support for Lattice RISC_V soft IP cores
Semidynamics announces, 4-way, Atrevido 423 RISC-V core
RISC-V Fast-Forwards, Breaks Ground for Auto Innovations
Want Tailormade Screamingly-High-Performance RISC-V64 IP?Fully customisable 4-way RISC-V core for big dataThe Power of RISC-V: DAC Panel with Intel, Imperas, Meta, OpenHW Group & Ventana
ANDLA DEBUTS FOR AI ACCELERATION
The Growing Momentum of RISC-V in Europe
YOLOX for Object Detection
SiFive’s WorldGuard Security Platform Now Available to the Entire RISC-V Ecosystem
Low-cost RISC-V BL616 module supports TinyMLRISC-V Bytes: Timer InterruptsReal-Time RISC-V-Based CAN-FD Bus Diagnosis Tool
Andes Unveils Details of its Entry Level D23 RISC-V Processor Core
Bluespec collaborates with Synopsys to address growing verification demands for RISC-V design community
Andes Webinar 2023 | Andes President and CTO, Dr. Charlie Su, Andes Technology
RISC-V Reaches a Turning Point | James Sanders and Wayne Lam, CCS Insights
Removing the Risk from RISC-V using the RISC-V Trace Standard | Peter Shields, Siemens
El Correo Libre Issue 58 | Gareth Halfacree, FOSSSi Foundation
Espressif ESP32-P4 – A 400 MHz general-purpose dual-core RISC-V microcontroller | Jean-Luc Aufranc, CNX Software
Everyone deserves a Pinecil | Chris Person, The Verge
My open source silicon highlights of 2022 and goals for 2023 | Matt Venn, Zero To ASIC Course
Ashling announce RiscFree™ support for MachineWare’s SIM-V RISC-V Instruction Set Simulator.Limerick, Ireland. 29th May 2023 - Ashling announced today that Ashling’s RiscFree SDK now provides target debug support for MachineWare’s SIM-V RISC-V Instruction Set Simulator.…
Semidynamics announces fully customisable, 4-way, Atrevido 423 RISC-V coreThe Atrevido 423 has a wider, 4-way pipeline, allowing for the decoding and retirement of up to two times more instructions than its recently launched,…
RiscFree C/C++ support for Lattice RISC_V soft IP coresAshling has added support for RISC-V soft IP cores from Lattice Semiconductor to its RiscFree development tool. The RiscFree software development kit (SDK) includes an…
Semidynamics announces, 4-way, Atrevido 423 RISC-V coreSemidynamics has launched the next member of its Atrevido family of 64-bit cores. The Atrevido 423 h... Read more at: https://www.bisinfotech.com/semidynamics-announces-4-way-atrevido-423-risc-v-core/
RISC-V Fast-Forwards, Breaks Ground for Auto InnovationsThe SiFive RISC-V Automotive CPU IP continues to advance to address and enable automotive applications like infotainment, connectivity and advanced driver-assistance systems. Yet without the…
Want Tailormade Screamingly-High-Performance RISC-V64 IP?Soooo… you’ve decided you’re going to create a system-on-chip (SoC) device of such awesomeness that it will leave your competitors gnashing their teeth and rending…
Fully customisable 4-way RISC-V core for big dataSemidynamics in Spain has developed a customisable 4-way RISC-V 64bit core for data centre chips. The Atrevido 423 RISC-V core has a wide 4-way pipeline…
The Power of RISC-V: DAC Panel with Intel, Imperas, Meta, OpenHW Group & VentanaRISC-V was one of the key themes at DAC 2023. We had a RISC-V Zone where six members discussed their latest RISC-V activities, and there…
ANDLA DEBUTS FOR AI ACCELERATIONAndes’ new deep-learning accelerator addresses convolutional neural networks in edge applications. Accompanied by vector CPUs, it forms an AI subsystem that can be scaled up…
The Growing Momentum of RISC-V in EuropeBy: Kezia Leung The RISC-V Summit Europe brought together members of the RISC-V community from industry, government, research, and academia to explore how RISC-V is…
YOLOX for Object DetectionAuthor: Meng Chang This topic presents an example about how to deploy a YOLOX model on a RISC-V development board for object detection. The content…
SiFive’s WorldGuard Security Platform Now Available to the Entire RISC-V EcosystemData and codes are only as powerful as the security platform that protects them. Without a robust security model for isolated code execution and data…
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Low-cost RISC-V BL616 module supports TinyMLSipeed launched today two embedded devices based on the RISC-V BL616 microcontroller from Bouffalo Lab. The M0S module is enabled with WiFi6, Bluetooth 5.2 and Zigbee interfaces in…
RISC-V Bytes: Timer InterruptsOperating systems do great work, but sometimes they need a little bit of help to know when to switch from one task to another. Thankfully,…
Real-Time RISC-V-Based CAN-FD Bus Diagnosis ToolNetwork Diagnosis Tools with industrial-grade quality are not widely available for common users such as researchers and students. This kind of tool enables users to…
Andes Unveils Details of its Entry Level D23 RISC-V Processor CoreAt the RISC-V Summit last month, Andes Technology announced its new D23 entry-level RISC-V processor core to the industry. At the time, there was not much truly known about…
Bluespec collaborates with Synopsys to address growing verification demands for RISC-V design communityFRAMINGHAM, MASS. (PRWEB) JANUARY 11, 2023 Bluespec Inc., announced today a collaboration with Synopsys to provide Synopsys reference methodologies for verification and hardware/software debug of…
Andes Webinar 2023 | Andes President and CTO, Dr. Charlie Su, Andes TechnologyAndes Webinar is the annual opportunity to get the information about RISC-V technology trends, innovative Andes solutions and more. Andes President and CTO, Dr. Charlie…
RISC-V Reaches a Turning Point | James Sanders and Wayne Lam, CCS InsightsRISC-V, introduced in 2010, is the first novel instruction set architecture (ISA) to gain market traction in decades. New design firms such as SiFive —…
Removing the Risk from RISC-V using the RISC-V Trace Standard | Peter Shields, SiemensWith the growing maturity of the RISC-V ISA, chip companies now have a wealth of options for implementing RISC-V cores in their latest product. At…
El Correo Libre Issue 58 | Gareth Halfacree, FOSSSi FoundationPreparations Begin for Latch-Up 2023 The FOSSi Foundation is very pleased to announce that Latch-Up will go ahead in 2023! This marks a triumphant return…
Espressif ESP32-P4 – A 400 MHz general-purpose dual-core RISC-V microcontroller | Jean-Luc Aufranc, CNX SoftwareEspressif ESP32-P4 is a general-purpose dual-core RISC-V microcontroller clocked at up to 400 MHz with AI instructions extension, numerous I/Os, and security features. It also…
Everyone deserves a Pinecil | Chris Person, The VergeLearning to solder was a life-changing experience for me, but it can seem daunting. You aren’t just screwing and unscrewing parts — you are melting…
My open source silicon highlights of 2022 and goals for 2023 | Matt Venn, Zero To ASIC CourseMy favourite moments of 2022 and goals and thoughts for 2023! Watch the full video.