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Takeaways From the First RISC-V Summit Europe
VIDEO: Running LVGL Application on RT-Smart MicroKernel OS with RISC-V
The growth of RISC-V across industries
Imperas Helps Navigate the Journey to RISC-V Based Silicon at DAC 2023
Takeaways From the First RISC-V Summit Europe
RISC-V Summit Europe 2023: Highlights from Barcelona
The Next Revolution in the Microchip Industry
HPCpodcast: An Architecture Update from RISC-V International CTO Mark Himelstein
Power, automotive and AI markets highly interested in RISC-V
It’s all about RISC-V code size
Bluespec’s MCUX RISC-V Processor Ideal for FPGAs and ASICsVIDEO: EUPILOT: Europe’s HPC and AI pre-exascale accelerator demonstrator
Mouser Now Stocking Renesas Electronics RZ/Five-RISC-V Microprocessor for IoT Endpoint and Industrial Gateway Apps | ELE Times
RISC-V chip to drive next generation app store of hearables | Nick Flaherty, EENews Europe
What is the Titan M2 security chip in Google’s Pixel phones? | Calvin Wankhede, Android Authority
Arm’s push into cars ‘a logical step’ as competition grows from open-source RISC-V | Thomas Macaulay, The Next Web
Standardized Open-Source Processor Architecture | Jon Gabay, Mouser Electronics
Allwinner D1/D1s Platform Support Moves Closer To Mainline Linux | Michael Larabel, Phoronix
MProtect: Operating System Memory Management without Access | Caihua Li, Seung-seob Lee, Min Hong Yun, Lin ZhongA Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance | Yuhao Ju; Jie GuIP-Tag: Tag-Based Runtime 3PIP Hardware Trojan Detection in SoC Platforms | Kejun Chen; Orlando Arias; Xiaolong Guo; Qingxu Deng; Yier JinMcPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework | Jianwang Zhai; Chen Bai; Binwu Zhu; Yici Cai; Qiang Zhou; Bei YuGHAZI: An Open-Source ASIC Implementation of RISC-V based SoC | Zain Rizwan Khan, Wajeh ul Hasan, Zeeshan Rafique, Ali Ahmed Ansari, Syed Roomi Naqvi
How to reduce the risk when making the shift to RISC-V | Rupert Baines, Codasip
Takeaways From the First RISC-V Summit EuropeRISC-V, a free and open source instruction-set architecture (ISA), has gained significant traction from both industry giants and emerging startups. A simple, scalable design, coupled…
VIDEO: Running LVGL Application on RT-Smart MicroKernel OS with RISC-VRecap of the 2023 RT-Thread Global Tech Conference: Today, we’re excited to feature HIMA, a passionate engineer with experience in developing embedded systems. Currently pursuing…
The growth of RISC-V across industriesRISC-V has seen significant momentum during the past year. According to RISC-V International there are over 10 billion RISC-V cores on the market, with thousands…
Imperas Helps Navigate the Journey to RISC-V Based Silicon at DAC 2023Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced its participation at DAC 60 with panels and presentations, and exhibits and…
Takeaways From the First RISC-V Summit EuropeRISC-V, a free and open-source instruction set architecture (ISA), has gained significant traction from both industry giants and emerging startups. A simple, scalable design, coupled…
RISC-V Summit Europe 2023: Highlights from BarcelonaMore than 500 attendees, from across the world, attended the first-ever RISC-V Summit Europe Last month, the first-ever RISC-V Summit Europe happened in Barcelona, Spain.…
The Next Revolution in the Microchip IndustryAs microchips increasingly become an integral part of our lives, share prices for many companies that make them are rising fast. Last week shares of…
HPCpodcast: An Architecture Update from RISC-V International CTO Mark HimelsteinMark Himelstein, chief technology officer at RISC-V International, joins us to discuss the latest developments with the RISC-V instruction set architecture and its growing community and…
Power, automotive and AI markets highly interested in RISC-VAt the recent SiFive RISC-V China Technology Forum that took place in Shenzhen, China, SiFive chief architect and the chairman of RISC-V International Krste Asanović…
It’s all about RISC-V code sizeHere at Codasip we’re passionate about reducing the code size of our RISC-V cores for our customers, but why? Are we not making the core…
Bluespec’s MCUX RISC-V Processor Ideal for FPGAs and ASICsFramingham, Massachusetts. Bluespec Inc. released its MCUX RISC-V processor designed to simplify the integration of customize protocols and add accelerators to FPGAs and ASICs. The platform…
VIDEO: EUPILOT: Europe’s HPC and AI pre-exascale accelerator demonstratorThe EUPILOT project aims to establish a European-based accelerator platform for high-performance computing (HPC) and AI. It seeks to achieve European digital sovereignty in HPC, promote the adoption of the RISC-V…
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Mouser Now Stocking Renesas Electronics RZ/Five-RISC-V Microprocessor for IoT Endpoint and Industrial Gateway Apps | ELE TimesMouser Electronics, the industry’s leading New Product Introduction (NPI) distributor with the widest selection of semiconductors and electronic components, is now stocking the RZ/Five-RISC-V microprocessor…
RISC-V chip to drive next generation app store of hearables | Nick Flaherty, EENews EuropeUS startup Sonical Sound Solutions is launching an ‘app store’ for headphones and hearables at CES this week ahead of a high performance, low power…
What is the Titan M2 security chip in Google’s Pixel phones? | Calvin Wankhede, Android AuthorityWith the Pixel 6 series, Google began developing its in-house Tensor SoC. But that wasn’t the first time the search giant used a piece of custom…
Arm’s push into cars ‘a logical step’ as competition grows from open-source RISC-V | Thomas Macaulay, The Next WebChip designer Arm is rapidly expanding its automotive business, amid mounting competition from open-source rival RISC-V. Revenue from the segment has doubled since 2020, the Financial Times reports.…
Standardized Open-Source Processor Architecture | Jon Gabay, Mouser ElectronicsHow often have we had to learn a new processor architecture and development environment because our new project requires more horsepower and speed than previous…
Allwinner D1/D1s Platform Support Moves Closer To Mainline Linux | Michael Larabel, PhoronixThe D1 is Allwinner's first SoC based on a RISC-V core design. While the Allwinner D1 isn't powerful at all, it's appearance in low-cost boards,…
MProtect: Operating System Memory Management without Access | Caihua Li, Seung-seob Lee, Min Hong Yun, Lin ZhongModern operating systems (OSes) have unfettered access to application data, assuming that applications trust them. This assumption, however, is problematic under many scenarios where either…
A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance | Yuhao Ju; Jie GuAbstract: While neural network (NN) accelerators are being significantly developed in recent years, CPU is still essential for data management and pre-/post-processing of accelerators in…
IP-Tag: Tag-Based Runtime 3PIP Hardware Trojan Detection in SoC Platforms | Kejun Chen; Orlando Arias; Xiaolong Guo; Qingxu Deng; Yier JinAbstract: The complexity of modern system-on-chip (SoC) designs and the ever shortened time-to-market (TTM) makes the third-party intellectual property (3PIP) a cornerstone in the modern…
McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework | Jianwang Zhai; Chen Bai; Binwu Zhu; Yici Cai; Qiang Zhou; Bei YuAbstract: Power efficiency has become a nonneglected issue of modern CPUs. Therefore, accurate and robust power models are highly demanded in academia and industry. However,…
GHAZI: An Open-Source ASIC Implementation of RISC-V based SoC | Zain Rizwan Khan, Wajeh ul Hasan, Zeeshan Rafique, Ali Ahmed Ansari, Syed Roomi NaqviAbstract—Due to the closed source, expensive nature of digitaldesign tools and licensing cost of System on Chip (SoC) IPsfor ASIC, the hardware industry lacks innovation…
How to reduce the risk when making the shift to RISC-V | Rupert Baines, CodasipWith the Intel® Pathfinder for RISC-V* program, Intel launched a development environment that enables companies of all sizes to start their RISC-V journey. Codasip makes its L31 RISC-V…