No recent posts listed
Tiempo Secure’s new TESIC RISC-V IP successfully passes SERMA CC EAL5+ security assessment tests
VMware join hands with Samsung, AMD, RISC-V for confidential computingTiempo Secure’s new TESIC RISC-V IP successfully passes SERMA CC EAL5+ security assessment tests
VMware, Other Tech Giants Announce Push for Confidential Computing Standards
Customizable RISC-V processor is vendor-independent
Chinese Researchers Used AI to Design RISC-V CPU in Under 5 Hours
VMware, AMD, Samsung and RISC-V push for confidential computing standardsVMware partners with Samsung, AMD and RISC-V to accelerate confidential computing
The Call for Papers for RISC-V Summit China 2023 is Open
China Mobile releases two self-developed RISC-V communications chips
The European Project Creating Extensible, Energy-Efficient RISC-V CPUs
Tailor Made RISC-V Performance – eeNews interview with Roger Espasa/Semidynamics
From RISC-V to 3D NAND Technology—Looking Back at the Trends of 2022 | Kimber Wymore, All About Circuits
Year 2022 in review – Top 10 posts and statistics | Jean-Luc Aufranc, CNX Software
RISC-V on the Final Frontier | Embedded Computing Design Staff, Embedded Computing DesignBouffalo Lab BL616/BL618 RISC-V MCU supports WiFi 6, Bluetooth 5.2, and Zigbee | Jean-Luc Aufranc, CNX Software
Lichee RV 86 Panel Getting Started Guide | James A. Chambers, Legendary Technology BlogBSC Develops 4 Open-Source Hardware Components Based on RISC-V | HPC Wire
Tencent joins open-source chip design community RISC-V as China seeks to mitigate impact from US sanctions | Che Pan, South China Morning Post
Adapting To Broad Shifts Essential In 2022 | Brian Bailey, Semiconductor EngineeringRISC-V Pushes Into The Mainstream | Marie C. Baca and Ed Sperling, Semiconductor EngineeringServer-class RISC-V Core Unveiled by Ventana at RISC-V Summit | Aaron Carman, All About CircuitsEfficient Trace In RISC-V | Ed Sperling, Semiconductor Engineering
How RISC-V has become a viable third processor architecture | Dean Takahashi, Venture Beat
Tiempo Secure’s new TESIC RISC-V IP successfully passes SERMA CC EAL5+ security assessment testsGrenoble, France – July 3, 2023 – Tiempo Secure’s latest TESIC design, a Secure Element targeting applications such as iSIM, eSE, Payment, UWB, Digital ID, IoT…
VMware join hands with Samsung, AMD, RISC-V for confidential computingVMware recently announced at the Confidential Computing Summit 2023 that it is partnering with chipmakers Samsung, AMD, and the RISC-V Keystone community for a project to help accelerate…
Tiempo Secure’s new TESIC RISC-V IP successfully passes SERMA CC EAL5+ security assessment testsGrenoble, France – July 3, 2023 – Tiempo Secure’s latest TESIC design, a Secure Element targeting applications such as iSIM, eSE, Payment, UWB, Digital ID, IoT…
VMware, Other Tech Giants Announce Push for Confidential Computing StandardsIn conjunction with the 2023 Confidential Computing Summit last week, VMware announced a partnership with tech giants to accelerate the development of confidential computing applications.…
Customizable RISC-V processor is vendor-independentBluespec’s MCUX RISC-V processor allows developers to implement custom instructions and add accelerators to FPGAs and ASICs. MCUX joins the company’s MCU RISC-V family of…
Chinese Researchers Used AI to Design RISC-V CPU in Under 5 HoursA group of Chinese scientists has published (PDF) a paper titled "Pushing the Limits of Machine Design: Automated CPU Design with AI." The paper details the researchers'…
VMware, AMD, Samsung and RISC-V push for confidential computing standardsVMware has joined AMD, Samsung, and members of the RISC-V community to work on an open and cross-platform framework for the development and operation of…
VMware partners with Samsung, AMD and RISC-V to accelerate confidential computingVMware Inc. stepped up its efforts to accelerate the adoption of confidential computing today, announcing an alliance with chipmakers Samsung Electronics Co. Ltd. and Advanced Micro Devices Inc., as…
The Call for Papers for RISC-V Summit China 2023 is OpenRISC-V Summit China is a major international event to share technical and business innovation around RISC-V. The global event brings together the community for a…
China Mobile releases two self-developed RISC-V communications chipsChina Mobile recently released the world's first LTE-Cat.1 chip with pure self-developed RISC-V architecture, as well as its first pure self-developed mass-production cellular IoT communications…
The European Project Creating Extensible, Energy-Efficient RISC-V CPUsSome European researchers are developing open-source RISC-V cores to compete with x86 and Arm, and are relying on only €8 million in funding. Details about…
Tailor Made RISC-V Performance – eeNews interview with Roger Espasa/SemidynamicsThe RISC-V Instruction Set Architecture is perfectly suitable for fine tuning the performance depending on the application. In this interview Roger Espasa, CEO and Founder…
No recent posts listed
No recent posts listed
No recent posts listed
No recent posts listed
From RISC-V to 3D NAND Technology—Looking Back at the Trends of 2022 | Kimber Wymore, All About CircuitsCatch up on some of the technology and industry trends we’ve noticed from 2022. This last year, 2022, has been filled with tons of new…
Year 2022 in review – Top 10 posts and statistics | Jean-Luc Aufranc, CNX SoftwareIt’s the last day of the year and the time to look at some of the highlights of 2022, some traffic statistics from CNX Software…
RISC-V on the Final Frontier | Embedded Computing Design Staff, Embedded Computing DesignOn this Episode of Embedded Insiders we’re joined by Founder and CTO of Croquet, David Smith, to discuss the company’s Portals technology which is designed to securely…
Bouffalo Lab BL616/BL618 RISC-V MCU supports WiFi 6, Bluetooth 5.2, and Zigbee | Jean-Luc Aufranc, CNX SoftwareBouffalo Lab BL616/BL618 is a 32-bit RISC-V wireless microcontroller with support for 2.4 GHz WiFi 6, Bluetooth 5.2 dual-mode, and an 802.15.4 radio for Zigbee,…
Lichee RV 86 Panel Getting Started Guide | James A. Chambers, Legendary Technology BlogThe Lichee RV 86 Panel is a RISC-V powered Linux computer complete with screen! It comes as a low cost kit with everything you need…
BSC Develops 4 Open-Source Hardware Components Based on RISC-V | HPC WireGreater performance demands of safety-critical, real-time systems require hardware and software components that can integrate the complexity required while adhering to stringent safety verification processes.…
Tencent joins open-source chip design community RISC-V as China seeks to mitigate impact from US sanctions | Che Pan, South China Morning PostTencent Holdings is the latest Chinese tech firm to join RISC-V International, the world’s largest open-source processor architecture group, as China faces growing US exports…
Adapting To Broad Shifts Essential In 2022 | Brian Bailey, Semiconductor EngineeringEvery year holds a number of surprises, and change provides an opportunity to innovate and gain advantage over those who are slower to adapt. Change…
RISC-V Pushes Into The Mainstream | Marie C. Baca and Ed Sperling, Semiconductor EngineeringOpen-source processor cores are beginning to show up in heterogeneous SoCs and packages. RISC-V cores are beginning to show up in heterogeneous SoCs and packages,…
Server-class RISC-V Core Unveiled by Ventana at RISC-V Summit | Aaron Carman, All About CircuitsIn a bid to bring RISC-V to the high-performance, data center computing space, Ventana announced their Veyron family, a series of processors positioned to offer…
Efficient Trace In RISC-V | Ed Sperling, Semiconductor EngineeringSystems with RISC-V cores often include multiple types of other processors and accelerators. Peter Shields, product manager for Tessent at Siemens Digital Industries Software, talks…
How RISC-V has become a viable third processor architecture | Dean Takahashi, Venture BeatThe economy and the event business aren’t strong, but the RISC-V Summit drew about 1,000 people to San Jose, California, this week to hear the latest on…