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PINE64 Star64: New single-board computer orderable with RISC-V processor
India RISC-V gets lift from Tenstorrent JV with Bodhi Computing
Taking control of data centres is a low-RISC move
Star64 Is Now Available to Order as PINE64’s First RISC-V SBCTenstorrent Announces Strategic RISC-V Ecosystem Development Partnership with Bodhi Computing Bodhi Computing
Adapting OpenTitan for open source FPGA prototyping and tooling development
[PODCAST] Making Formal Verification the New Normal in IoT with Ashish Darbari – Founder, Axiomise | The IoT Podcast
Announcing the Nerds Talking to Nerds About RISC-V event hosted by Tenstorrent | TenstorrentA dual-core TEE security solution based on E902
Renesas launches RISC-V voice recognition chip
Canonical Enables Ubuntu on Microchip’s PolarFire® SoC FPGA
LLVM 17 Lands Initial Support For RISC-V Vector Crypto Extension ISA
Researchers Build a RISC-V Chip That Calculates in Posits, Boosting Accuracy for ML Workloads | Gareth Halfacree, Hackster.io
Framework Based On An RISC-V Microprocessor Supporting LiM Operations | Coluccio, A.; Ieva, A.; Riente, F.; Roch, M.R.; Ottavi, M.; Vacca, M. RISC-Vlim, Semiconductor EngineeringAcceleration Robotics Partners with PlanV for a Robotics-Specific Open Source RISC-V Microcontroller | Gareth Halfacree, Hackster.io
Google experiments with RISC-V | Nick Farrell, Fudzilla
The Automotive Space Gears Up to Take on RISC-V | Murray Slovick, Electronic DesignST to make European octacore RISC-V space chip with selectable cores | Nick Flaherty, EE News Europe
Arm vs RISC-V? Which One Is The Most Efficient? | Gary ExplainsNative RISC-V ROS chip targets robotics | Nick Flaherty, EE News Europe
SiFive RISC-V cores picked for Google AI compute nodes | Dan Robinson, The Register
Google deploys SiFive’s Intelligence X280 processor for AI workloads | Sebastian Moss, Data Center DynamicsCodasip joins OpenHW to push RISC-V verification | Nick Flaherty, EE News Europe
ARM IS THE NEW RISC/UNIX, RISC-V IS THE NEW ARM | Timothy Prickett Morgan, The Next Platform
PINE64 Star64: New single-board computer orderable with RISC-V processorPINE64, which recently introduced the PineTab2 and PineTab-V, has started selling a new RISC-V-based single-board computer (SBC). Announced last year, the Star64 relies on the StarFive JH7110 SoC,…
India RISC-V gets lift from Tenstorrent JV with Bodhi ComputingIndia received a boost to its RISC-V program this week as Tenstorrent announced its investment in and partnership with Bodhi Computing, a company set up…
Taking control of data centres is a low-RISC moveIn the early 1990s, each passing year seemed to bring a new CPU architecture. Exotic chips such as Hobbit, PA-RISC, MIPS, Sparc, PowerPC and Alpha…
Star64 Is Now Available to Order as PINE64’s First RISC-V SBCStar64, PINE64’s first RISC-V single-board computer (SBC), is now available to order in two variants with 4GB and 8GB RAM and some impressive specs. Powered…
Tenstorrent Announces Strategic RISC-V Ecosystem Development Partnership with Bodhi Computing Bodhi ComputingBENGALURU, India, April 5, 2023 /PRNewswire/ -- Tenstorrent is excited to announce its continued commitment to India's Digital India RISC-V Program with its investment in and partnership with Bodhi Computing. Bodhi…
Adapting OpenTitan for open source FPGA prototyping and tooling developmentAntmicro’s projects often involve helping companies address their specific processing, security and other needs through designing and prototyping ASIC solutions with open source tools and…
[PODCAST] Making Formal Verification the New Normal in IoT with Ashish Darbari – Founder, Axiomise | The IoT PodcastAbout this Episode In season 3 episode 6 connect with Ashish Darbari – Founder & CEO at Axiomise to discover how formal verification is being…
Announcing the Nerds Talking to Nerds About RISC-V event hosted by Tenstorrent | TenstorrentTenstorrent, a leading AI semiconductor company, is proud to announce its upcoming RISC-V event in India. The event will be an excellent opportunity to immerse…
A dual-core TEE security solution based on E902Jiacheng Yang, Yahui Teng, Bingquan Huang Guangdong University of Technology In the China Postgraduate IC Innovation Competition this August, T-Head sponsored the design challenge: Building…
Renesas launches RISC-V voice recognition chipRenesas Electronics has developed its first RISC-V microcontroller designed for voice recognition interfaces systems using IP from Andes. The R9A06G150 32bit application specific processor (ASSP) provides…
Canonical Enables Ubuntu on Microchip’s PolarFire® SoC FPGACanonical published the optimized Ubuntu release for the first RISC-V based System-on-Chip (SoC) field-programmable gate array (FPGA)—our PolarFire® SoC FPGA Icicle Kit, expanding support for…
LLVM 17 Lands Initial Support For RISC-V Vector Crypto Extension ISAMerged this weekend to the LLVM 17 development code-base is initial support for RISC-V's vector crypto extension ISA. The latest LLVM (17) Git code has…
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Researchers Build a RISC-V Chip That Calculates in Posits, Boosting Accuracy for ML Workloads | Gareth Halfacree, Hackster.ioDesigned as an alternative to floating-point numbers, posits may prove key to boosting machine learning performance. A team of scientists at the Complutense University of…
Framework Based On An RISC-V Microprocessor Supporting LiM Operations | Coluccio, A.; Ieva, A.; Riente, F.; Roch, M.R.; Ottavi, M.; Vacca, M. RISC-Vlim, Semiconductor EngineeringA new technical paper titled “RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures” was published by researchers at Politecnico di Torino (Italy), Univerity of Tor Vergata…
Acceleration Robotics Partners with PlanV for a Robotics-Specific Open Source RISC-V Microcontroller | Gareth Halfacree, Hackster.ioDesigned specifically for ROS 2, the roscore-v RISC-V microcontroller promises reduced latencies and new real-time capabilities. Performance-boosting specialist Acceleration Robotics has announced a partnership with…
Google experiments with RISC-V | Nick Farrell, FudzillaSiFive RISC-V chips are being used by Google to run some of its AI workloads and tested in Google datacentres. SiFive's Intelligence X280 is a multi-core…
The Automotive Space Gears Up to Take on RISC-V | Murray Slovick, Electronic DesignSiFive is creating a lineup of compute IP for MCUs, MPUs, and soon, SoCs, as well as vector-processing solutions tailored for automotive applications. The first…
ST to make European octacore RISC-V space chip with selectable cores | Nick Flaherty, EE News EuropeSpace system designer CAES has built the first eight core fault tolerant chip that is selectable between different architectures, including RISC-V. The radiation hardened GR765 System-on-Chip (SoC)…
Arm vs RISC-V? Which One Is The Most Efficient? | Gary ExplainsArm has been making power efficient processors for decades. RISC-V is relativity new and many parts of its specifications aren't even ratified, but that hasn't…
Native RISC-V ROS chip targets robotics | Nick Flaherty, EE News EuropeTwo European companies are developing a microcontroller chip using the open source RISC-V instruction set that is optimised to run the latest Robot Operating System…
SiFive RISC-V cores picked for Google AI compute nodes | Dan Robinson, The RegisterCor, that's a shot in the arm for this upstart CPU ISA RISC-V chip biz SiFive says its processors are being used to manage AI…
Google deploys SiFive’s Intelligence X280 processor for AI workloads | Sebastian Moss, Data Center DynamicsGoogle is using the RISC-V-based SiFive Intelligence X280 processor in combination with the Google TPU, as part of its portfolio of AI chips. Fabless chip…
Codasip joins OpenHW to push RISC-V verification | Nick Flaherty, EE News EuropeGerman RISC-V core designer Codasip has joined the OpenHW group to push for advances in the verification of RISC-V cores. Codasip has highlighted issues with…
ARM IS THE NEW RISC/UNIX, RISC-V IS THE NEW ARM | Timothy Prickett Morgan, The Next PlatformWhen computer architectures change in the datacenter, the attack always comes from the bottom. And after more than a decade of sustained struggle, Arm Ltd…