We Created a Single Source for All RISC-V Specifications

Specifications are the lifeblood of RISC-V. These formal documents define everything from core behavior and privilege levels to interrupt handling, debug, platform software contracts, and binary compatibility.

As an open standard, the RISC-V instruction set architecture (ISA) gives anyone the ability to design and build custom silicon, with broad compatibility delivered at the application level through the RVA23 profile. For developers already familiar with other RISC ISAs, the barrier to entry is often comfortably low; so long as they can access the specs and documentation they need.

Yet while these specifications have always existed, they were hosted in various GitHub repositories, draft pages, and mailing lists, each maintained independently and published in different formats. As a result, it hasn’t always been easy to track specifications in their path from development to ratification.

Introducing the RISC-V Ratified Specifications Library

Which is why today, I’m very happy to announce that the RISC-V Ratified Specifications Library is live. It’s the product of almost a year of hard work from RISC-V International’s documentation team (being me and senior documentation architect Kersten Richter) consolidating and curating all of our available specifications into one single, accessible repository.

The Library contains every ratified RISC-V specification to date, organized into logical groupings, in both HTML and PDF formats. So whether you’re a chip designer reaching for the Privileged ISA or a software engineer hunting down the Supervisor Binary Interface spec, you’ll now find everything you need, all in one place.

Given the many Git repositories that make up the RISC-V organization, alongside the adoption several years ago of AsciiDoc as the markup language of choice for all specifications, it made sense for us to leverage the Antora static site generation tool. Antora is specifically architected to support multi-repository content sources, which made it a natural fit for aggregating content from across the RISC-V GitHub organization into a single coherent site. In other words, this is a major step up in terms of UX than anything we’ve had before.

The playbook repository my team uses to maintain and build docs.riscv.org can be found at antora.riscv.org on GitHub, and we welcome contributions and issue reports from the community.

Here’s a look at what’s available and what each specification covers:

Profiles

RISC-V Profiles

Defines the base profile framework for RISC-V, establishing a structured approach to grouping extensions into named, versioned profiles. This document provides the conceptual foundation and guidance on which implementations can base conformance claims.

RVA23 Profile

RVA23 represents a major milestone for the RISC-V ecosystem, defining a set of mandatory extensions for application processors. For the first time, OS vendors and software developers have a stable, predictable baseline they can confidently target, reducing fragmentation and enabling broader software portability. With RVA23-compliant hardware expected any day now, this profile sets the stage for a new generation of consistent, software-ready RISC-V platforms.

RVB23 Profile

The companion profile to RVA23, tailored for embedded, IoT and edge devices. RVB23 defines the requirements for resource-constrained implementations, making it a critical reference for firmware engineers and developers targeting microcontroller-class RISC-V platforms.

Hardware

Advanced Interrupt Architecture (AIA)

Defines the next-generation interrupt management framework for RISC-V, superseding the basic local interrupt scheme. AIA specifies how hardware and software collaborate to route, prioritize, and manage interrupts across complex, multi-hart systems with high scalability.

Input/Output Memory Management Unit (IOMMU)

Specifies the architecture, register interface, queues, and integration requirements for RISC-V IOMMUs. This specification enables secure and efficient DMA from peripherals and accelerators in systems with virtualization or strict memory isolation requirements.

Platform Level Interrupt Controller (PLIC)

Describes the programming model and behavioral requirements for the PLIC, RISC-V’s standard external interrupt controller. This specification is the go-to reference for software configuring interrupt priorities and routing on most current RISC-V SoCs.

Server SoC

Defines the mandatory requirements and conventions for building server-class RISC-V SoCs. This specification ensures hardware compatibility and sets a consistent bar for features like memory hierarchy, interrupt infrastructure, and management interfaces expected in datacenter deployments.

Debug, Trace, and RAS

Efficient Trace for RISC-V

Specifies the compressed trace architecture that captures instruction execution with minimal bandwidth overhead. This is the core trace format specification for RISC-V, enabling powerful profiling, debugging, and performance analysis workflows.

QoS Register Interface

Defines the register-level interface for controlling shared resource capacity and bandwidth on RISC-V platforms. The specification allows software to assign quality-of-service attributes to workloads, improving predictability in mixed-criticality systems.

RAS Error Record Interface (RERI)

Specifies how reliability, availability, and serviceability (RAS) error records are structured and accessed on RISC-V hardware. RERI gives firmware and operating systems a standardized mechanism to detect, log, and respond to hardware faults.

Debug Specification

Defines the external debug interfaces for RISC-V processors, covering the Debug Module, abstract commands, and hardware trigger mechanisms. This specification is essential for anyone building or integrating RISC-V debug probes and tooling.

Unformatted Trace & Data Encapsulation

Specifies the encapsulation format used to package raw trace data emitted by RISC-V hardware. This layer sits between the trace source and transport infrastructure, ensuring consistent framing regardless of the trace type.

N-Trace

Defines Nexus-based trace data formatting and transport for RISC-V. N-Trace provides an alternative to the E-Trace format, offering compatibility with industry-standard Nexus trace infrastructure widely used in embedded development environments.

Trace Connectors

Specifies the physical and logical connector definitions for RISC-V trace interoperability. This specification allows tooling vendors and hardware designers to produce probe and connector hardware that works consistently across RISC-V implementations.

Trace Control Interface (TCI)

Defines the software-visible control and configuration interface for RISC-V trace features. The TCI allows system software to start, stop, and configure trace sessions in a standardized way, independent of the underlying trace architecture.

Platform Software

Semihosting

Specifies the semihosting interface that allows software running on a RISC-V target to perform I/O operations on a connected host during development and debugging. An invaluable tool during early bring-up, before a platform’s native I/O infrastructure is operational.

Boot and Runtime Services (BRS)

Defines the software interface requirements for boot-time and runtime services on RISC-V platforms. BRS establishes what system firmware must provide to operating systems, covering the handoff contract that enables portable OS support across diverse hardware.

Functional Fixed Hardware (FFH)

Specifies the FFH interface definitions used by ACPI-based platforms to describe RISC-V-specific hardware behaviors. This document enables ACPI firmware to expose RISC-V features in a standardized way to operating systems and management software.

IO Mapping Table (RIMT)

Defines a standardized ACPI table format for describing how I/O devices are mapped to IOMMUs on RISC-V platforms. The RIMT enables OS software to correctly configure DMA isolation and address translation for connected peripherals.

Platform Management Interface (RPMI)

Specifies the messaging protocol and service definitions for RISC-V platform management. RPMI provides a structured mechanism for application processors to communicate with platform microcontrollers for power management, performance control, and other platform services.

Supervisor Binary Interface (SBI)

Defines the standard firmware interface between supervisor-mode software (operating systems and hypervisors) and the underlying machine-mode firmware. SBI is one of the most widely implemented RISC-V specifications and is essential for any software targeting Linux or other OS environments.

UEFI Protocol

Specifies the RISC-V-specific UEFI protocols that define the software interface between operating systems and platform firmware. This document ensures that RISC-V platforms can participate fully in the UEFI firmware ecosystem used across server and desktop environments.

Application Enablement

Application Binary Interface (ABI)

This defines the ABI conventions for RISC-V ELF binaries, including calling conventions, register usage, and data layout. This specification is the key reference for compiler and toolchain developers producing or consuming RISC-V binaries.

Vector C Intrinsics

Specifies the C language intrinsics for programming the RISC-V Vector extension. This document is the definitive guide for developers who want to harness RISC-V vector capabilities directly from C code without dropping into assembly.