Hardware

Using a Performance Model to Implement a Superscalar CVA6

How We’re Using AI to Streamline RISC-V Regression Debugging

AI verification startup Verifaix explains how its AI Debug Agent automates regression debugging, helping RISC-V developers reduce manual verification effort and accelerate design cycles.

Ocelot3: Full Vector “V” Extension for BOOM

Optimizing Hardware for Neural Network Inference using Virtual Prototypes

Europe Achieves a Key Milestone with the Europe’s First Out-of-Order RISC-V Processor chip, with the eProcessor Project

The eProcessor Project today announced the successful development and deployment of the Europe’s first out-of-order RISC-V processor silicon. The processor, manufactured in a 22nm process, represents a leap forward in...

CVA6 RISC-V PMP Vulnerabilities against FIA

Learning Computer Architecture with a Visual Simulation of RISC-V Processors

TYRCA: A RISC-V Tightly-Coupled Accelerator For Code-Based Cryptography

HaDes-V – Learning by Puzzling: A Modular Approach to RISC-V Processor Design Education

TestRIG – Randomized Testing of RISC-V CPUs