Vector and Hypervisor extensions are key mandatory components of the RVA23 Profile, addressing math-intensive workloads including AI/ML & cryptography, and enterprise hardware, operating systems and software workloads Santa Clara, Calif.…
Message from RISC-V International The countdown is on! RISC-V Summit North America takes place on October 22-23 at the Santa Clara Convention Center. The Summit is a must-attend event for professionals…
Industry Veteran Brings Software and Hardware Experience to Role Guiding all RISC-V Technical Activities MUNICH, Germany – June 24, 2024 – RISC-V International, the global open standards organization, announced that…
Message from RISC-V International Events are key to the success of RISC-V, where we come together to share the latest developments and build the relationships that move our ecosystem forward. …
On May 18th RISC-V is turning 14! To celebrate we are giving away 14 bundles of the RISC-V Fundamentals Course and RISC-V Foundational Associate Certification (RVFA). We would love to…
MEDIA ALERT: Calista Redmond, CEO of RISC-V International, to Speak at ESD Alliance 2024 CEO Executive Outlook WHO: Calista Redmond, CEO of RISC-V International WHAT: RISC-V International CEO Calista Redmond…
Latest Ratifications Primarily Target Core Areas of Efficiency, Vector, and Virtualization ZURICH – April 4, 2024 – RISC-V International, the global standards organization, today announced that 40 new technical specifications…
WHO: RISC-V International WHAT: RISC-V International will be exhibiting at embedded world 2024, sharing the latest developments from its community and showcasing a range of development boards inside the booth.…
Message from RISC-V International 2024 is now well underway and we have some exciting new developments from our members worldwide! RISC-V is truly a global ecosystem, and last month we…
Message from RISC-V International As we look back on 2023, we wanted to express our gratitude to the entire RISC-V ecosystem. Throughout the year, we witnessed groundbreaking developments, new product…
RISC-V adoption continues to expand across key vertical markets including aerospace, AI/ML, automotive, data center, embedded, HPC, and security Santa Clara, Calif. – Nov. 7, 2023 – At the RISC-V…
Message from RISC-V International Greetings! We’re in the final countdown to RISC-V Summit North America, which runs Nov. 6-8 in Santa Clara, CA. The anticipation and excitement across the ecosystem are…
Message from RISC-V International RISC-V is inevitable! During the past few months, the RISC-V ecosystem has continued to grow globally. We are witnessing incredible adoption, activity, and momentum across a…
Message from RISC-V International The growth and reach of the RISC-V ecosystem continues to inspire me during 2023! We are seeing incredible adoption across a huge number of applications and…
Embedded World, Mar-14 2023, Nuremberg, Germany. Ashling and Imagination Technologies announced today that Ashling’s RiscFree SDK will provide software development support for Imagination’s Catapult RISC-V-based IP cores. RTXM-2200 is the…
RISC-V Momentum We’re off to an incredible start in 2023! We have already ratified several extensions and are on course to complete six ratifications in the first quarter including Profiles.…
First-ever RISC-V Summit Europe Will Demonstrate Technical and Commercial Momentum Across Industries
The Barcelona RISC-V Summit from June 5-9 to focus on industries such as Automotive, High Performance Compute/Data Center, and Security; Call for Submissions and Sponsorships now open BARCELONA, Spain…
Recipients Selected from Tens of Thousands of Engineers Working on RISC-V Initiatives Globally San Jose, Calif. – Dec. 21, 2022 – RISC-V International, the global open standards organization, announced the…
RISC-V Summit brings together the global RISC-V community after a banner year San Jose, Calif. – Dec. 13, 2022 – RISC-V International, the global open standards organization, highlighted the community’s…
Call for Proposals, Sponsorship Sales, and Attendee Registration Now Open Event Spans December 12th through 15th; Summit Sessions Are December 13th and 14th San Francisco – July 29, 2022…
Efficient Trace, Supervisor Binary Interface, Unified Extensible Firmware Interface, and Zmmul Multiply-Only Extension Accelerate Embedded- and Large-System Design. Six Additional Specifications Already In the Pipeline As Development Extends Into Vertical…
RISC-V welcomes Intel to the Board of Directors to collaborate on RISC-V IP and contribute engineering expertise to accelerate RISC-V software development ZURICH – February 7, 2022 – RISC-V International,…
With billions of chips in the market, RISC-V has seen widespread commercial adoption across industries and implementations, from embedded automotive to hyperscale AI, from 5G to HPC and beyond. Zurich…
Ventana will continue to contribute and accelerate technical progress and market adoption of RISC-V ZURICH – Dec. 6, 2021 – RISC-V International, a global open hardware standards organization, today announced that…
RISC-V International Ratifies 15 New Specifications, Opening Up New Possibilities for RISC-V Designs
New Vector, Scalar Cryptography and Hypervisor specifications will help accelerate the adoption of RISC-V across a variety of market segments. ZURICH – Dec. 2, 2021 – RISC-V International, a global…
Founded in Collaboration with the CHIPS Alliance, OpenPOWER Foundation, and Western Digital, the Alliance is Focused on Providing Support Programs, Learning Opportunities, and Mentoring for Women and Underrepresented Individuals in…
ZURICH and SAN FRANCISCO – July 28, 2021 – RISC-V International announced the 2021 RISC-V Summit that will bring together the open hardware community for three days of deep technical…
SAN FRANCISCO, May 5, 2021 – Today, the seL4 Foundation and RISC-V International announced that the verified seL4 microkernel on the RV64 architecture has been proved down to the executable…
Investment firm Chengwei Capital to join the RISC-V Board of Directors and Technical Steering Committee Zurich – April 29, 2021 – RISC-V International, a non-profit corporation controlled by its members…
New joint working group will enhance the OmniXtend Cache Coherency architecture SAN FRANCISCO, March 24, 2020 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption…
The online courses are offered on edX.org and will make RISC-V training more accessible SAN FRANCISCO - EMBEDDED WORLD - March 2, 2021 – The Linux Foundation, the non-profit organization…
RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension Fast Track significantly accelerates the ratification of small architecture extensions Zurich – Feb. 23, 2021 – RISC-V International,…
RISC-V Innovation Founders Awards In recognition of the industry impact initiated by the technical leadership and generous contribution of the founding inventors and innovators of the RISC-V ISA. 2020 RISC-V…
Silicon startup Stream Computing to join the RISC-V Board of Directors and Technical Steering Committee to advance open source AI innovation Zurich – Dec. 8, 2020 – RISC-V International, a…
RISC-V sees widespread commercial adoption across industries, from embedded to AI, from IoT to HPC and beyond Zurich – Dec. 8, 2020 – RISC-V International, a non-profit corporation controlled by…
The leading RISC-V conference will be held virtually this year, featuring keynotes, tutorials, exhibitions, networking opportunities and more WHAT: The RISC-V International Association has announced the online program for the…
The schedule for RISC-V Global Forum is live! We have an exciting lineup of keynotes, session presentations, lightning talks, ask the experts, sponsor exhibits, and networking opportunities. Below you can…
Industry associations collaborate to drive open source standards that simplify security design for hardware developers and enhance the security of IoT devices and processors May 11, 2020 – GlobalPlatform, the…
Ratification signifies another breakthrough for the thriving RISC-V ecosystem San Francisco – March 9 2020 – The RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption…
Redmond joins the RISC-V Foundation from IBM to continue to grow RISC-V membership, community engagement and market adoption The RISC-V Foundation, a non-profit corporation controlled by its members to drive the…
Innovation has accelerated with the rapid development of the RISC-V ecosystem The RISC-V Foundation, a non-profit corporation controlled by its members to drive a new era of processor innovation via…
When: 9:30 – 10 CET Who: Robert Oshana, NXP Semiconductors RISC-V is an open hardware ISA. It's gaining a lot of traction in the industry. Many companies are now asking…
中國烏鎮--(美國商業資訊)--今日在中國浙江烏鎮舉行的世界互聯網大會 (World Internet Conference) 上，RISC-V基金會(RISC-V Foundation)宣布任命半導體業資深人士方之熙 (Jesse Zhixi Fang)博士為RISC-V基金會新成立的中國顧問委員會主席。RISC-V 基金會是一家由會員管理的非營利組織，致力於促進免費開放原始碼的 RISC-V 指令集架構 (ISA) 的應用與實施。RISC-V 基金會在中國的影響力不斷擴大，涵蓋超過 25 個機構和大學，在此基礎上，中國顧問委 員會將對 RISC-V 基金會的教育與應用推廣策略提供指導意見，以進一步加快推行 RISC-V 生態系統在該地區的發展。方之熙博士將與當地相關人士密切合作，並在中國的RISC-V 社群招賢納士，邀請業界精英加入委員會。
中国乌镇- (美国商业资讯)--今天在中国乌镇举行的世界互联网大会(World Internet Conference)上，RISC-V基金会(RISC-V Foundation)宣布，半导体行业资深人士方之熙(Jesse Zhixi Fang)博士已被任命为RISC-V基金会新组建的中国顾问委员会主席。RISC-V基金会是一家由其成员所管理的非营利组织，致力于促进免费开源的RISC-V指令集架构(ISA)的应用与实施。RISC-V基金会在中国的影响力不断扩大，覆盖超过25个组织机构与大学，在此基础上，中国顾问委员会将对RISC-V基金会的教育与应用推广战略提供指导意见，以进一步加速RISC-V生态系统在该地区的发展。方之熙博士将与当地利益相关方密切合作，并在中国的RISC-V社区招贤纳士，邀请一些重要人士加入委员会。
We’re seeking proposals for talks and poster presentations conveying recent activity in the RISC-V community at the upcoming RISC-V workshop co-hosted by Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya…
When: 9:30 a.m. – 10 a.m. CET Who: Tim Morin, Microsemi Corporation In this presentation we will demonstrate both open source and commercial RTOS available for RISC-V. The attendees will…
Our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus…
This will be a three day event broken down as follow: Tuesday and Wednesday November 28-29, 2017 - These two days will follow our traditional two day format used at…
Submission Guidelines: Submission abstracts should consist of at most two pages in pdf format, and must include the title, authors, and affiliations. Additional material can be appended to the submission…
The preliminary agenda for the 6th RISC-V Workshop, co-hosted by NVIDIA and the Shanghai Jiao Tong University (SJTU) in Shanghai China on May 8-11, 2017 is shown below. As with past workshops,…
Registration and the call for presentations / posters for the 6th RISC-V Workshop, co-hosted by NVIDIA and the Shanghai Jiao Tong University (SJTU) in Shanghai China on May 8-11, 2017 is now…
Registration remains open and the call for presentations / posters is now closed for the 5th RISC-V Workshop, hosted at Google’s Quad campus (468 Ellis Street, Mountain View, CA 94043)…
Registration remains open and the call for presentations / posters is now closed for the 5th RISC-V Workshop, hosted at Google’s Quad campus (468 Ellis Street, Mountain View, CA 94043)…
Registration is now open for our 4th RISC-V Workshop which will be hosted at MIT's Computer Science and Artificial Intelligence Lab (CSAIL) building this coming July 12-13, 2016. The goals…
The RISC-V team was out in force at the HotChips-26 conference manning a sponsor booth. ...more... The Berkeley RISC-V team pose for a group shot at the end of the conference. From…
As we were getting ready for HotChips, we realized we were missing something very important: A logo! Thanks to the creative designers at 99designs, we were able to get a…
Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
Semiconductor veterans secure $3.7M seed funding to launch a universal RISC-V processor that eliminates the need for specialized chips, enabling advanced AI at no additional cost in embedded systems by…
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How RISC-V standards are changing the world [Q&A]
You may have heard of RISC-V -- usually pronounced 'risk-five' -- it's an instruction set architecture originally designed to support computer architecture research and education but which has evolved to…
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Interview with Calista Redmond, CEO, RISC-V International
Could you give us an overview of RISC-V's mission and why it's expanding so rapidly, with over 4,500 members across 70+ countries? RISC-V's rapid growth aligns with the increasing demand…
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RISC-V for HPC at SC24
RISC-V is an open Instruction Set Architecture (ISA), where the ISA can be thought of as the contract between the software and hardware worlds. Since RISC-V was first released around a decade…
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Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Esperanto Technologies™, a leading developer of RISC-V chips and software for high-performance computing (HPC) and artificial intelligence (AI), today announced that they are cooperating with NEC Corporation…
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Openchip, NEC and Barcelona Supercomputing Center studying Collaboration to develop Next Generation Supercomputers based on RISC-V
Barcelona / Tokyo, 14 of November 2024 –Openchip, NEC and the Barcelona Supercomputing Center are studying collaboration to develop the new Openchip Vector Computing Accelerator for use in supercomputing data…
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DeepComputing Launches Early Access Program for DC-ROMA RISC-V Mainboard for Framework Laptop 13
DeepComputing is excited to announce the launch of an exclusive early access program for the DC-ROMA RISC-V Mainboard, specifically designed for industry and business customers. This limited-edition initiative gives early…
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VIDEO: RISC-V Design Innovations with Custom Extensions | Synopsys
Andes and Synopsys present a ‘software first’ design flow using virtual platforms/prototypes allows RISC-V developers to explore new hardware configuration options with application SW workloads and full OS support. Watch…
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MIPS releases RISC-V CPU for autonomous vehicles
MIPS released its P8700 CPU based on the RISC-V computing architecture to target driver assistance and autonomous vehicle applications. The San Jose, California-based company, which focuses on developing efficient and configurable…
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The Convergence of Functional with Safety, Security and PPA Verification
Formal For All! “Do I need a PhD to use formal verification?” “Can formal methods really scale?” “Is it too difficult to write formal properties that actually prove something?” “If…
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Highlights from the RISC-V Summit 2024
What you’ll learn: The state of RISC-V, including new RISC-V announcements. A look at some good video presentations at the 2024 RISC-V Summit. RISC-V trends in 2025. I didn't make…
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Fractile Licenses Andes Technology’s RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI Inference
San Jose, CA — Oct. 22, 2024 — Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, are proud to announce…
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Interview with RISC-V International: High-Performance Chips, AI, Ecosystem Fragmentation, and The Future
RISC-V is an industry standard instruction set architecture (ISA) born in UC Berkeley. RISC-V is the fifth iteration in the lineage of historic RISC processors. The core value of the…
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RISC-V Oozes Confidence with RVA23 Profile Ratification
Last week’s RISC-V Summit in Santa Clara, Calif., had an air of confidence that we have not seen at previous summits. There was much for this tight-knit community to shout…
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4 Highlights From the RISC-V Summit North America
In this roundup, we discuss several announcements from last week's summit pushing RISC-V adoption and processing power. Four companies, including Andes Technology, RISC-V International, Arteris, and Codasip, made significant announcements…
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DeepComputing and Andes Technology Partner to Develop the World’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop
San Jose, CA — Oct 22, 2024 — DeepComputing, a pioneer in RISC-V innovation, today announced a strategic partnership with Andes Technology Corporation, a leading provider of high-efficiency, low-power 32/64-bit RISC-V processor cores. Together,…
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RISC-V User-Space Pointer Masking Appears Ready For Linux 6.13
It looks like the upcoming Linux 6.13 cycle will be adding RISC-V support for user-space pointer masking and tagged address ABI. RISC-V pointer masking can be used for implementing memory tagging akin…
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Denso seals Quadric deal for RISC-V AI core
Leading Japanese automotive supplier Denso is expanding its semiconductor business through a development license agreement for a Neural Processing Unit (NPU) AI core from Quadric in the US, adding its…
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RISC-V CPU demoed with RX 7900 XTX GPU in Debian Linux — AMD flagship GPU paired with Milk-V Megrez board and SiFive P550 cores
RISC-V firm Milk-V demonstrated that it can get AMD’s RX 7900 XTX graphics card to work on one of its RISC-V boards. The PC shown in the video uses Milk-V’s Megrez board,…
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Codasip Unveils L730 Automotive-Grade Embedded RISC-V Core
MUNICH, Germany, Oct 28, 2024 – Codasip has announced its new L730 core. Codasip L730 is a high-quality, high-performance embedded core that meets automotive safety and security needs enabling ISO/SAE 21434 and…
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Life Lessons from the First Half-Century of My Career
By: David Patterson I started my career at Hughes Aircraft in 1972 while working on my Ph.D. at the University of California, Los Angeles (UCLA). After designing airborne computers for…
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Nvidia to ship a billion of RISC-V cores in 2024
Although Nvidia's GPUs rely on proprietary CUDA cores that feature their instruction set architecture and support for various data formats, these cores are controlled by custom cores that rely on…
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Nvidia projected to ship roughly a billion RISC-V cores in its products by year’s end
In brief: Nvidia has been quietly using the RISC-V architecture to power numerous computing devices, and deploying a substantial number of cores to paying customers. In fact, the company is nearing…
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RISC-V reaches milestone with RVA23 profile ratification
The ratification of the RVA23 profile for RISC-V marks a monumental moment for the architecture, and anyone who's been following RISC-V knows that this isn't just a checkbox. RVA23 is…
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RVA23 Profile ratification bolsters RISC-V software ecosystem
RVA23 Profile, a major release for the RISC-V software ecosystem, has been ratified, and it’s expected to help accelerate widespread implementation among toolchains and operating systems. Before ratification, it underwent…
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Ashling and Embecosm Announce Optimized Software Development Toolchain for Akeana at RISC-V Summit North America, 2024
October 22, 2024 – Santa Clara, CA – Ashling and Embecosm are excited to announce their latest collaboration in delivering a comprehensive, optimized toolchain for Akeana’s range of high-performance RISC-V…
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SiFive HiFive Premier P550 Development Boards Now Shipping
The world’s highest performance RISC-V development board unlocks new opportunities for software developers to create the next era of RISC-V applications Santa Clara, Calif. – Oct. 21, 2024 – SiFive,…
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SEGGER’s Ozone offers enhanced debugging with RISC-V Semihosting
SEGGER has expanded the capabilities of its debugger and performance analyzer, Ozone by adding semihosting support for debugging RISC-V applications. This feature now enables RISC-V developers to use I/O to perform debugging…
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Optimizing the RISC-V Backend
Hello everyone! A month and a half ago, we wrote about the latest status of the RISC-V DynaRec (Dynamic Recompiler, which is the JIT backend of Box64) and shared the gratifying progress…
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Are IoT Hardware Vendors Finally Going Open Source?
The open-source revolution is expanding beyond software into hardware design. New microcontrollers from Microchip Technology and Espressif incorporate processors based on RISC-V—an open-source instruction set architecture challenging Arm’s dominance in connected devices. RISC-V,…
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Software-defined processors: the promise of RISC-V
It’s an exciting time to be involved in open source. Linux powers the world’s most critical devices, a story to which Red Hat has always been a champion. Today we…
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LDRA extends RISC-V support, adds QNX
LDRA has extended support for the RISC-V instruction set architecture (ISA) in its high assurance quality analysis and verification tool suite. The LDRA static analysis tools support emerging RISC-V implementations such as…
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CEO interview: Chips Act boost for RISC-V
Nick Flaherty talks to Calista Redmond, CEO of RISC-V International, on how the European Chips Act is driving the open instruction set architecture forward. “The recent European summit showed the…
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Synopsys RISC-V ARC-V processor IP gets Lauterbach debug and trace
Lauterbach has extended their industry leading TRACE32® debug and trace tools to include support for Synopsys’ RISC-V instruction set based ARC-V™ processor IP, which includes full debug and trace, including…
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Introducing fast RISC-V interrupts support in Renode for real time applications
Real time applications such as space or automotive where instant autonomous decision making is crucial require configurable standardized interrupt controllers. There are many well-known examples such as the Global Interrupt…
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KVM expansion card utilizes RISC-V CPU architecture for enhanced remote PC management — Sipeed NanoKVM-PCIe now available for pre-order starting at $40
Those looking for PC management solutions like KVMs, particularly in the server space, may be interested to hear of Sipeed's new KVM expansion card, which just opened up for preorders…
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RISC-V Summit to Feature, AI, Auto, RTOS and Many More Key Topics
The RISC-V Summit, North America will take place October 22-23, 2024 at the Santa Clara Convention Center in Santa Clara, California. According to RISC-V International, the organization supporting and defining the standards…
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[VIDEO] An Open-Source Project for High-Performance RISC-V Processors Meeting Industrial-Grade Standards
Speaker: Yungang Bao. Deputy Director, Institute of Computing Technology, Chinese Academy of Sciences. Chief Scientist, Beijing Institute of Open Source Chip. It is widely recognized that the open-source hardware ecosystem…
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[VIDEO] Accelerate your adoption of RISC-V with CORE-V-VERIF
CORE-V-VERIF is an open-source project supported by the OpenHW Group. Its goal is to provide an open-source environment and work-flow that can be deployed onto any RISC-V processor core. Since…
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TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor
By Wenbo Yin, Vice President of IC Design, TetraMem Inc. Introduction The rapid proliferation of artificial intelligence (AI) across a growing number of hardware applications has driven an unprecedented demand…
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Rivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoC
NX45 Becomes the Only RISC-V Core to Pass Rivos’ Rigorous Verification Process After Extensive Evaluation of Leading RISC-V Cores San Jose, CA – Sep. 11, 2024 — Rivos Inc., a RISC-V Premier…
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Andes Technology is Expanding RISC-V’s Horizons in High-Performance Computing Applications
By: Dr. Charlie Su, President and CTO, Andes Technology Corp. At Andes Technology, we are excited to share some of our latest advancements and insights into the growing role of RISC-V…
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[VIDEO] Accelerating RISC-V testbench development with open source RISC-V RTL and emulation
Today’s shorter product time to market makes silicon verification runway shorter. Tenstorrent is working on CPUs based on RISC-V architecture for many AI applications. Since this is an emerging processor…
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[VIDEO] A Holistic Approach to RISC-V Processor Verification
Processors using the open standard RISC-V instruction set architecture (ISA) are becoming more and more common, with an estimated 30% of SoCs designed in 2023 containing at least one RISC-V…
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[VIDEO] The Future of Compute
Patrick Little, SiFive Chairman, President and CEO talks about how RISC-V is shaping the future of compute, how SiFive is gaining momentum from applications from embedded to the datacenter and…
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Codeplay Brings RISC-V Support to the oneAPI Construction Kit
RISC-V is the fast growing, open standard instruction set architecture (ISA) for processors of all types including CPUs and accelerators. These processors can be utilized for a wide variety of…
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RISC-V is Built for Artificial Intelligence and SiFive Solutions for AI
RISC-V inventor and SiFive Founder Krste Asanovic discusses why RISC-V is "built for" AI applications and how SiFive is working from the edge to the datacenter to bring AI solutions…
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SiFive unveils RISC-V chip design for high-performance AI workloads
SiFive, a designer of chips based on the RISC-V computing platform, announced a series of new AI chips for high-performance AI workloads. The SiFive Intelligence XM Series is designed for…
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[VIDEO] RISC-V Taipei Day 2024 – Reshape the Future with AI
The development of AI computing has reached a critical inflexion point. Large-language models (LLMs) have attracted tremendous attention recently and require huge computations for AI model training and inference. In…
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VyperCore plans 5nm RISC-V server chip and card
VyperCore in Bristol is aiming to design and sell a 5nm chip and card for the server market to accelerate existing software. For this, VyperCore is ramping up recruitment of…
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Bitluni’s Magnetic LED Matrix Build Showcases Clever RISC-V Programming
YouTuber bitluni's latest incredible build video uses a RISC-V microcontroller with an uncommon driving technique to create a modular magnetic LED matrix. The LED matrix is an off-the-shelf 8x8 module. Bitluni…
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How RISC-V Changes the Global Landscape of AI and ML
The rise of Artificial Intelligence (AI) and Machine Learning (ML) has rapidly impacted today's global economy, influencing everything from healthcare to autonomous systems. As of 2023, 55% of organizations used…
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SiFive Highlights Key Inflection Points Driving RISC-V Adoption for AI and Introduces Intelligence XM Series for AI Workload Acceleration
Santa Clara, Calif. – Sept. 18, 2024 – Today, SiFive, Inc. the gold standard for RISC-V computing, announced the SiFive Intelligence™ XM Series designed for accelerating high performance AI workloads. This is…
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Accelerating RISC-V Processor Verification: A Co-Simulation Strategy
With RISC-V processor architectures gaining traction across diverse computing systems, ensuring their reliability through rigorous verification becomes more crucial than ever. We have embraced a robust co-simulation strategy for verifying…
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Lauterbach adds debug and trace support for Renesas 32-bit-RISC-V microcontrollers
Lauterbach's TRACE32® development tools now provide support for Renesas’s primary 32-bit RISC-V® general-purpose Microcontroller family, designed for cost-conscious and energy-efficient embedded applications. In addition to providing read and write access…
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[PODCAST] Pioneering RISC-V and Defining Software-Defined Vehicles
On this episode of Embedded Insiders, we’re joined by Calista Redmond, CEO of RISC-V International, and Andrea Gallo, VP of Technology, as they dive into the organization’s latest technical breakthroughs,…
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Tales from Beyond the Register Map
By: Olof Kindgren "A new SERV version! How much smaller than the last one?" Hate to disappoint you all, but we have now reached the point where the award-winning SERV, the…
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EDACafe Bunker Broadcast with Calista Redmond
Calista Redmond, CEO of RISC-V International, joins Sanjay Gangal of EDACafe to discuss the growth of RISC-V, the community, and the upcoming RISC-V Summit North America taking place on Oct…
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How RISC-V Changes the Global Landscape of AI and ML
The rise of Artificial Intelligence (AI) and Machine Learning (ML) has rapidly impacted today's global economy, influencing everything from healthcare to autonomous systems. As of 2023, 55% of organizations used…
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3 steps to shrinking your code size, your costs, and your power consumption
RISC-V is a powerful instruction set that is constantly evolving. One of the recent evolutions relates to code size reduction. Last year, the RISC-V Zc extensions were ratified. The team at Codasip…
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Olimex’s One-Euro RVPC Single-Board Computer Goes Up for Sale Next Week
Bulgarian open hardware specialist Olimex is gearing up to launch a RISC-V single-board computer that will cost around one dollar at retail — and while it's basic, it's enough to…
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TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor
The rapid proliferation of artificial intelligence (AI) across a growing number of hardware applications has driven an unprecedented demand for specialized compute acceleration not met by conventional von Neumann architectures.…
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Semidynamics on major recruitment drive for RISC-V software engineers
Barcelona, Spain – September 9, 2024. Semidynamics, the European RISC-V custom core AI specialist, is on a major recruitment drive for a wide range of engineers from junior to senior at its Barcelona…
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Wine Down Friday with RISC-V’s Calista Redmond
In this episode of Wine Down Friday, we are thrilled to welcome Calista Redmond, CEO of RISC-V International. Calista shares her journey from IBM to leading the charge at RISC-V,…
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RISC-V Builds the Backbone of Three New Consumer Devices
RISC-V, the open-standard ISA, has inspired a host of innovative designs in tablets, cameras, and laptops. In the past few years, RISC-V has transitioned from a project relegated to academia…
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Orange Pi Embraces RISC-V with the Raspberry Pi-Like Orange Pi RV Single-Board Compute
Joining the likes of PINE64, Geniatech, and Milk-V, Orange Pi announces a Raspberry Pi-like SBC built atop the StarFive JH7110. Single-board computer specialist Orange Pi has launched a new Raspberry…
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RISC-V Enables Performant and Flexible AI and ML Compute
The emergence of Artificial Intelligence (AI) and Machine Learning (ML) is one of the most significant computing trends in recent history. According to research, by 2027, spending on AI software…
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SiFive and Arkmicro Accelerate RISC-V Adoption in Automotive Electronics with SiFive’s Automotive IP for the High-end SoC Market
Santa Clara, Calif. - September 2, 2024 — Today SiFive, Inc. announced that it has licensed its SiFive Automotive RISC-V IP cores to Arkmicro Technologies (Shenzhen), accelerating the adoption of RISC-V in automotive…
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Jesse Taube Gets Linux Up and Running on the Raspberry Pi RP2350’s Hazard3 RISC-V Cores
Developer Jesse Taube has become the first to successfully boot a minimal Linux distribution on the Raspberry Pi Pico 2's RP2350 microcontroller — taking advantage of the chip's new open…
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RISC-V International N-Trace TG Milestone
The market is experiencing a major shift to the RISC-V ISA and MIPS is helping to fuel this transition with high performance RISC-V cores, including debug, trace and performance tools…
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Resiltech To Develop Test Libraries for Andes ASIL-D RISC-V Processor IP
Andes Technology in Taiwan has confirmed details of its deal with Italian software provider Resiltech for Software Test Libraries (STL) for automotive-grade RISC-V processor IP. The partnership, signed in December,…
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Resiltech and Andes Technology Announce Collaboration to Deliver Advanced STL Solutions for Andes Automotive-Grade RISC-V Processor IP
Pontedera, Italy and Hsinchu, Taiwan – Aug 29th, 2024 – Resiltech, a renowned provider of comprehensive security and safety solutions and services, and Andes Technology, a leading supplier of high-performance, low-power RISC-V processor…
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RISC-V World Tour; Munich, Hangzhou, Santa Clara…
Ian Ferguson from SiFive attended the RISC-V event in Hangzhou, China, in August 2024. Explore his insights on the event's impressive scale, vibrant atmosphere, and the practical "solve real problems"…
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SEALSQ Testing Its QS7001 RISC V Quantum-Resistant Platform
SEALSQ Testing its QS7001 RISC V Quantum-Resistant Platform I the Next Generation WISeSat Satellites; Prototype to Launch in November 2024 Geneva, Switzerland, Aug. 28, 2024 (GLOBE NEWSWIRE) -- The satellite,…
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C28 PQShield and SiFive Collaborate to Advance Post-Quantum Cryptography in RISC-V
LONDON and SANTA CLARA, Calif., Aug. 28, 2024 /PRNewswire/ -- PQShield, a leading quantum-safe cryptography provider, and RISC-V processing pioneer SiFive have partnered to deliver post-quantum cryptography on SiFive's Essential and Performance high-performance processor families, protecting critical aerospace, consumer, defense,…
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DeepComputing Opens Pre-Orders for the SpacemIT K1 RISC-V-Powered DC-ROMA RISC-V Pad II Tablet
RISC-V specialist DeepComputing has unveiled a new portable computing gadget, powered by the SpacemIT K1 system-on-chip: the DC-ROMA RISC-V Pad II tablet computer. "DeepComputing is excited to announce the official…
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Geniatech actively lays out RISC-V ecosystem to accelerate industrial IoT development
Recently, one of the world’s three major RISC-V professional exhibitions, the largest annual RISC-V event – 2024 RISC-V China Summit was held in Hangzhou, Zhe Jiang Province, RISC-V China Summit…
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reCamera modular AI camera features SG2002 RISC-V AI SoC, supports interchangeable image sensors and baseboards
Seeed Studio’s reCamera AI camera is a modular RISC-V smart camera system for edge AI applications based on SOPHGO SG2002 SoC. The camera is made up of three boards: the…
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XiangShan High-Performance RISC-V Processors at Hot Chips 2024
XiangShan is a RISC-V CPU project out of China, and now hosted on Github. This is a high-performance CPU design, instead of lower performance designs that we have seen from…
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Tenstorrent’s Blackhole Chips Boast 768 RISC-V Cores and Almost as Many FLOPS
Hot Chips RISC-V champion Tenstorrent offered the closest look yet at its upcoming Blackhole AI accelerators at Hot Chips this week, which they claim can outperform an Nvidia A100 in raw…
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New RISC-V Innovations Lead AI to Open Standard
If the growing number of new RISC-V announcements aren’t enough proof of the license-free protocol’s momentum, there is a mountain of analyst predictions, trend research, and market analysis that seems…
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[VIDEO] Join us for This Year’s RISC-V Summit
From the IoT edge to the depths of space, RISC-V enables groundbreaking innovations. Join us at the RISC-V Summit 2024, October 22–23, at the Santa Clara Convention Center to discover…
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SEALSQ introduces new RISC-V secure hardware platform for IoT security
With the need for more robust, quantum-resilient security the company’s new platform represents a significant advancement in securing critical data and infrastructure against the threats posed by quantum computing. The…
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DeepComputing Announces the Launch of the DC-ROMA RISC-V Pad II!
DeepComputing is excited to announce the official launch of the DC-ROMA RISC-V Pad II, a groundbreaking product designed to empower the RISC-V community with an advanced mobile terminal experience. By leveraging…
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Microchip unveils PIC64 family of RISC-V multicore processor chips for Earth and for space
Literally the day after writing the article about the Microchip PolarFire SoC Discovery Kit based on the company’s PolarFire SoC FPGA, Microchip gave me a preview of two closely related…
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[VIDEO] Checking Out The Teensy Tiny RISC-V NanoKVM!
Wendell checks out the NanoKVM. It's so tiny! Check it out here: https://sipeed.com/nanokvm Watch the video.
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Harnessing power of RISC-V, Generative AI: Expert hardware security architect Avani Dave’s vision
The convergence of RISC-V architecture and generative AI is paving the way for revolutionary advancements in hardware security. These technologies promise to enhance the resilience of systems against an array…
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RISC-V cluster IP for data centre SoCs and chiplets
Called P870-D, it is an update of the non-data centre P870, with support added for AMBA CHI protocol. “By harnessing a standard CHI bus,” said SiFive, “the P870-D enables SiFive’s…
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SiFive moves into RISC-V datacentre AI processor IP
SiFive has modified its high end RISC-V core for more scalability in datacentre AI chip designs. The P870-D datacentre RISC-V IP is a variant of the previous P870 so that it scales…
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Akeana exits stealth mode with comprehensive RISC-V processor portfolio
With the support from A-list investors including Kleiner Perkins, Mayfield, and Fidelity the company has announced the formal availability of its expansive line of IP solutions that are customisable for…
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SiFive Announces New High-performance RISC-V Datacenter Processor for Demanding AI Workloads
Santa Clara, Calif., Aug. 14, 2024 – Today SiFive, Inc., the gold standard for RISC-V computing, announced its new SiFive PerformanceTM P870-D datacenter processor to meet customer requirements for highly parallelizable…
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With $100M raised, Akeana unveils new RISC-V chip designs
Akeana, the company trying to change semiconductor design, has raised over $100 million in funding in the past three years to design RISC-V processors. Now it’s launching products. Today’s launch…
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Raspberry Pi Launches New RP2350 MCU and Pico 2 Dev Board with RISC-V Support
Starting with the release of Raspberry Pi Model B in 2012, Raspberry Pi has a history of innovation with a strong focus on user experience. Their expansion port designs enable…
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Akeana exits stealth mode with comprehensive RISC-V processor portfolio, challenging the semiconductor industry status quo
Akeana™, the company committed to driving dramatic change in semiconductor IP innovation and performance, has announced its official company launch approximately three years after its foundation, having raised over $100 million in…
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[VIDEO] Synopsys & TASKING RISC-V Solutions for Safety & Security Critical Automotive Apps
Learn how designers benefit from the combination of TASKING's VX Toolset for RISC-V and Synopsys ARC-V™ IP, by gaining access to tools to develop safe, secure, and power-efficient SoCs for…
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deepin 23丨RISC-V New Era Leading Desktop Operating System Innovation
Academician Ni Guangnan of the Chinese Academy of Engineering has stated that the RISC-V architecture, due to its openness and flexibility, has become one of the most popular choices in…
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[VIDEO] Raspberry Pi RP2350 – New Microcontroller Chip with Arm CPUs and RISC-V CPUs 🤯
The Raspberry Pi people have released a new microcontroller board the Raspberry Pi Pico 2. However the star of the show is the new microcontroller chip, the RP2350. It upgrades…
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Raspberry Pi launches its first RISC-V multicore chip
Raspberry Pi has stepped up its chip development with a quad core microcontroller with two ARM Cortex-M33 cores and two in-house RISC-V cores. The $5 Raspberry Pi Pico 2 board…
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Raspberry Pi Launch New RP2350 Microcontroller and Pico 2 Development Board with RISC-V Support
Raspberry Pi is one of the most recognisable brands of single board computers, created as an affordable way to promote the teaching of computer science to young people, to give…
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[VIDEO] Developing the RISC-V Framework Laptop Mainboard
Nirav & Hyelim sit down at Framework HQ SF to talk about all things RISC-V and DeepComputing. RISC-V Mainboard: https://frame.work/products/deep-comp... Read the blog post: https://frame.work/blog/introducing-a... Watch the full video.
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Canonical Adds Microchip’s New PIC64GX to Its List of Ubuntu-Supported RISC-V Platforms
Canonical has announced another new entry in its growing list of RISC-V platforms for which an official Ubuntu Linux image is available, launching an image for Microchip's new PIC64GX family…
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Leveraging Safety Processor Expertise to Develop RISC-V Based Automotive Implementations
The podcast interview explores the role of RISC-V in the automotive sector. It begins with a brief introduction to RISC-V, explaining it as an open standard instruction set architecture (ISA). The…
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Wuhan Sets Up Open-Source RISC-V Innovation Hub for Next-Gen Chips
(Yicai) July 26 -- Central Chinese city of Wuhan has formed a new innovation hub for RISC-V, an open-source instruction set architecture used to design chips. The hub will commit…
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Lauterbach Supports Microchip’s PIC64GX RISC-V® MPUs
Hoehenkirchen, Germany—July 25, 2024 — Lauterbach’s TRACE32® development tools now support Microchip’s 64-bit RISC-V® PIC64GX microprocessor family for power-efficient embedded-compute platforms. TRACE32® tools support includes simultaneous debugging of the RISC-V…
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Ashling announces RiscFree™ C/C++ SDK support for Microchip Technologies’ PIC64GX RISC-V ® -based multicore MPUs
July-23rd , 2024, Limerick, Ireland. Embedded tools developer Ashling is pleased to partner with Microchip Technology, supporting the new and innovative PIC64GX RISC-V based multicore MPUs with our RiscFree™ C/C++…
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Imagination Technologies announces new capital investment from Fortress Investment Group
Imagination Technologies (“Imagination”) today announced a new investment by funds managed by affiliates of Fortress Investment Group LLC (“Fortress”). Under the terms of the agreement, Fortress has provided Imagination with a…
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Microchip Unveils Industry’s Highest Performance 64-bit HPSC Microprocessor (MPU) Family for a New Era of Autonomous Space Computing
CHANDLER, Ariz., JULY 9, 2024 — The world has changed dramatically in the two decades since the debut of what was then considered a trail-blazing space-grade processor used in NASA missions…
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Ashling announces RiscFree™ C/C++ SDK support for India’s C-DAC VEGA RISC-V-based Multi-core Microprocessors
July-8 th, 2024, Kochi, India. Embedded tools developer Ashling is pleased to partner with C-DAC, supporting their VEGA RISC-V based multi-core microprocessor family with our RiscFree™ C/C++ SDK and Opella-XD…
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Trillions of Cycles per Day: How SiFive Boosts IP and Software Validation with Synopsys HAPS Prototyping System
In today’s landscape of generative AI, IoT, and more, the demand for advanced RISC-V core IP is rapidly escalating. As technology becomes increasingly software-driven, the industry has shifted from developing…
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How Early Power Analysis Drives Energy-Efficient RISC-V Designs
In the world of processor development, flexibility is becoming a distinct advantage. As an open-standard instruction set architecture (ISA), the fifth iteration of reduced instruction set computing (RISC-V) embodies this…
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Axelera AI Raises $68 Million Series B Funding to Accelerate Next-Generation Artificial Intelligence
Silicon Valley, CA and Eindhoven, NL – June 27, 2024 – Axelera AI, the leading provider of purpose-built AI hardware acceleration technology for generative AI and computer vision inference, today announced…
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RISC-V Shows Ambitious Prospects in Europe
Munich, Germany — The European tech landscape is witnessing a notable evolution with the growing embrace of RISC-V, the open-source instruction set architecture. During the recent RISC-V Summit Europe, leading…
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Tenstorrent’s RISC-V-based Wormhole AI accelerators are available for pre-order today — pre-built workstations start at $12,000
AI start-up Tenstorrent has announced the commercial release of its Wormhole processors, built to power AI accelerators to compete with Nvidia. Wormhole will power the new Wormhole n150 and n300…
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Unpacking the CanMV K230 RISC-V board
RISC-V ISA is almost 15-year old and RISC-V hardware has been popping up regularly for a while. Until recently it was difficult to find a board with RISC-V Vector support, in particular…
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RISC-V power controller adds flash memory
Eggtronic in Italy has added reprogrammable flash memory to its EPIC RISC-V mixed-signal power controller. The Eggtronic RISC-V EPIC 2.0 Flash series provides more flexibility through the design process, while…
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DAC 2024 – Showcasing the future of RISC-V through EDA
As I sat on the plane in Boston it’s fair to say that I was curious about what DAC 2024 would bring. The previous year was much better than I…
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Navigating the RISC-V Ecosystem
The open-source RISC-V instruction set continues to make inroads across the electronics industry. Electronic Design’s and Microwaves & RF’s Bill Wong offer his take on the current status and future…
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Microchip starts 64bit PIC64 family with RISC-V
Microchip has launched its first 64bit microprocessor line, starting with a multicore RISC-V cluster for its PIC64GX family. The PIC64 GX1000 uses the existing RISC-V four core cluster with a…
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RISC-V, the Linux of the chip world, is starting to produce technological breakthroughs
A decade ago, an idea was born in a laboratory at the University of California at Berkeley to create a lingua franca for computer chips, a set of instructions that…
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RISC-V Fosters Collaboration in the Chip Race
The RISC-V ecosystem has witnessed significant global investment, particularly from China, which is increasingly positioning itself as a pivotal player in the open-source semiconductor manufacturing landscape. In an exclusive interview…
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[VIDEO] RISC V Ecosystem Panel | Open Source is Transforming AI and Hardware
2024 ANDES RISC-V CON Silicon Valley DEEP DIVE INTO AUTOMOTIVE / AI / APPLICATION PROCESSORS AND SECURITY TRENDS Recently, RISC-V, with its open, streamlined, and scalable configuration, has become the…
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[VIDEO] RISC V Ecosystem Panel | Unlocking the RISC V Application Processor Potential
2024 ANDES RISC-V CON Silicon Valley DEEP DIVE INTO AUTOMOTIVE / AI / APPLICATION PROCESSORS AND SECURITY TRENDS Recently, RISC-V, with its open, streamlined, and scalable configuration, has become the…
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SEALSQ RISC-V Semiconductors is Pioneering Sustainability Through Decentralized Processing
SEALSQ Corp ("SEALSQ" or "Company") (NASDAQ: LAES), a leader in developing and selling semiconductors, PKI, and post-quantum technology hardware and software products, announces the breakthrough adoption and future potential of…
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Microchip Technology Expands Processing Portfolio to Include Multi-Core 64-bit Microprocessors
CHANDLER, Ariz., July 9, 2024 — Real-time, compute intensive applications such as smart embedded vision and Machine Learning (ML) are pushing the boundaries of embedded processing requirements, demanding more power-efficiency, hardware-level security…
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Microchip Unveils Industry’s Highest Performance 64-bit HPSC Microprocessor (MPU) Family for a New Era of Autonomous Space Computing
CHANDLER, Ariz., JULY 9, 2024 — The world has changed dramatically in the two decades since the debut of what was then considered a trail-blazing space-grade processor used in NASA…
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Microchip Now Offers Full Microprocessor Spectrum, From 8- to 64-bit MPUs
With the ability to shift computing resources as needed, Microchip’s new 64-bit, RISC-V processors bring needed flexibility to embedded edge devices. Microchip has announced two new multi-core 64-bit MPUs operating…
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Breker Brings RISC-V Verification to the Next Level #61DAC
RISC-V is clearly gaining momentum across many applications. That was quite clear at #61DAC as well. Breker Verification Systems solves challenges across the functional verification process for large, complex semiconductors.…
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Eight core RISC-V processor and TSN switch for AI space designs
Microchip is qualifying an eight core fault tolerant RISC-V processor for AI in space applications. The radiation tolerant PIC64-HSPC octal core 1.2GHz switch provides 26K DMIPS and is built on…
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Microchip starts 64bit PIC64 family with RISC-V
Microchip has launched its first 64bit microprocessor line, starting with a multicore RISC-V cluster for its PIC64GX family. The PIC64 GX1000 uses the existing RISC-V four core cluster with a…
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RISC-V Thrives Through Research, International Collaboration
Munich, Germany — During the recent RISC-V Summit Europe, EE Times had the opportunity to talk to a leading RISC-V researcher Frank Kagan Gürkaynak, a senior scientist at ETH Zürich…
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Stealth startup Vybium developing European RISC-V AI accelerator
European startup Vybium is developing am AI accelerator chip using the open RISC-V instruction set architecture to take on the Nvidia A100 GPU in the data centre. Vybium is a…
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[VIDEO] M5: RISC-V Instruction Set Architecture | RISC CPU Performance Explained
In this course, our Founder and CEO, Mr. P R Sivakumar, explains the layered architecture of RISC-V open ISA and how we chip designers design various chips like simple embedded…
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DAC 61: EDA addressing growing system complexity
At this year’s Design Automation Conference (DAC), I was told that the committee had received some 1,500 technical paper and presentation submissions, and a 34% increase in research paper submissions,…
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Introducing the Mini-ITX motherboard ‘Milk-V Jupiter’ equipped with a RISC-V processor
Milk-V , a developer of RISC-V-related hardware, has announced the Milk-V Jupiter, a Mini-ITX motherboard equipped with a RISC-V processor. Milk-V Jupiter | RISC-V PC for Everyone https://milkv.io/jupiter RISC-V is…
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Desk of Ladyada – It’s a RISC-V kinda weekend #DeskOfLadyada #Adafruit
This weekend we ended up working a lot on two RISC-V designs in a push to get the final PCBs out the door. First up is the CH32v203 QT Py.…
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RISC-V Summit Europe 2024
Germany was buzzing this week. No, not because of the Euros. Munich also hosted the 2024 edition of the RISC-V Summit Europe, and Codethink was in town! RISC-V Summit Europe…
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[VIDEO] RISC-V NAS: BPI-F3 & OpenMediaVault
RAID RISC-V NAS built using a Banana Pi BPI-F3 single board computer and a JMB582 PCIe to SATA adapter. Watch the video.
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Sunny skies and electric energy: RISC-V Summit Europe 2024 shines in Munich
This week, the 2024 edition of RISC-V Summit Europe took place in lovely Munich, Germany. Those of us who attended last year’s edition in Barcelona might not have expected the…
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RISC-V Summit Europe News—Processor IP, Verification Tools, and More
At every point in the design process, RISC-V developers can make use of the advancements presented at RISC-V Summit Europe. It’s been a big week for open-source processors as the…
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SiFive Essential Product Family Expanded at the RISC-V Summit Europe
Munich, Germany. SiFive, Inc. announced an innovative design of its SiFive Essential product family at the RISC-V Summit Europe 2024. With over a decade of development, the Essential IP has demonstrated…
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RISC-V Verification: From Simulation To Formal
Axiomise’s Nicky Khodadad and Ashish Darbari discuss simulation and the need for formal verification and RISC-V, including why simulation-based verification is inadequate to find all the bugs in a design…
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SiFive announces 4th-gen of popular essential product line to spur innovation across embedded applications
SiFive is seeing growing adoption, with more than two billion SiFive RISC-V-based chips already in the market. SiFive, Inc. the gold standard for RISC-V computing, unveiled a major upgrade of…
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Accelerate RISC-V Verification Using Synopsys Cloud
RISC-V is an emerging choice for semiconductor companies to create highly differentiated products for a wide range of end applications. Both established players and start-up companies are investing heavily and…
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Developers Use RISC-V Stack Without Worrying About Local SRAMs, DMAs
Semidynamics Tensor Unit efficiency data for its “All-In-One” AI IP, which uses a LlaMA-2 7B-parameter Large Language Model (LLM), has been made public. Roger Espasa, Semidynamics’ CEO, explained, “The traditional…
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ESWIN Computing Pairs SiFive CPU, Imagination GPU and In House NPU in Latest RISC-V Edge Computing SoC
Combining IP from two RISC-V leaders with an independently developed NPU brings advanced AI acceleration and rich user interfaces to ESWIN Computing’s EIC77 Series SoCs. June 25, 2024 -- Today,…
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RISC-V Summit: SiFive’s 4th generation embedded cores
SiFive announced the 4th generation of RISC-V CPU cores for embedded applications at RISC-V Summit Europe 2024 today. There are eight cores, three of which are 32bit while the other…
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DAC 2024 Day One: Designing Chiplets and AI with RISC-V
Watch the first of our roundups from DAC 2024, taking place this week at the Moscone Center in San Francisco, where we talk about the EDA, tools and support for…
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Semidynamics benchmarks 7bn parameter model on RISC-V AI IP
Spanish RISC-V IP developer Semidynamics has benchmarked the performance of its Tensor Unit running a LlaMA-2 7B-parameter Large Language Model (LLM) on an ‘all in one’ RISC-V AI IP core.…
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X-Silicon Introduces the World’s First Vulkan Driver Implementation for RISC-V, Enabling an entire Ecosystem of 3D Graphics, AI and Compute for Low-Power, Mobile, Edge and IOT Devices
SAN DIEGO, June 25, 2024 /PRNewswire/ -- X-Silicon is demonstrating the 1st Vulkan™ Software Rendering Platform capability running on the RISC-V Architecture. This opens up a new segment of low-power…
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SiFive Announces 4th Generation of Popular Essential Product Line to Spur Innovation Across Embedded Applications
SiFive is seeing growing adoption, with more than two billion SiFive RISC-V based chips already in the market Munich, Germany, June 25, 2024 – Today SiFive, Inc. the gold standard for…
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Semidynamics benchmarks 7bn parameter model on RISC-V AI IP
Spanish RISC-V IP developer Semidynamics has benchmarked the performance of its Tensor Unit running a LlaMA-2 7B-parameter Large Language Model (LLM) on an ‘all in one’ RISC-V AI IP core…
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Ashling announces RiscFree™ C/C++ SDK support for Renesas’s RISC-V-based R9AG021 MCUs
June-24 2024, RISC-V European Summit, Munich, Germany. Embedded tools developer Ashling today announced support for the Renesas R9AG021 RISC-V MCUs from Renesas in Ashling’s RiscFree software development kit (SDK) and…
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Industry Veteran Brings Software and Hardware Experience to Role Guiding all RISC-V Technical Activities
MUNICH, Germany – June 24, 2024 – RISC-V International, the global open standards organization, announced that Andrea Gallo has joined as the organization’s new vice president of Technology. Gallo heads…
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RISC-V International Names Andrea Gallo as VP, Technology
Industry Veteran Brings Software and Hardware Experience to Role Guiding all RISC-V Technical Activities MUNICH, Germany – June 24, 2024 – RISC-V International, the global open standards organization, announced that Andrea Gallo…
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Ventana CEO to Deliver a Keynote at RISC-V Summit Europe
Veyron Solution — World’s Highest Performance Data RISC-V Processor and Platform — Will Be Showcased Throughout Event CUPERTINO, Calif. – June 24, 2024 – Ventana Micro Systems Inc., provider of…
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[VIDEO] Road to testing applications on RISC-V with QEMU and Fedora – DevConf.CZ 2024
RISC-V is an open standard instruction set architecture that has potential to be widely used as an alternative to existing ARM and x86 solutions. For the software developers it's beneficial…
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Andes Technology Showcases Leadership in AI and Automotive Applications at RISC-V Summit Europe 2024
Industry-leading RISC-V solutions and live demonstrations of CPU IP are all on display at Booth #8. Discover the latest advancements from Andes’ presentations and posters! Munich, Germany – June 21,…
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Breker Verification Systems Readies RISC-V CoreAssurance and SoCReady SystemVIP for Automated, Certification-level RISC-V Verification Coverage
SAN JOSE, Calif., June 20, 2024 (GLOBE NEWSWIRE) -- Breker Verification Systems, whose product portfolio solves challenges across the functional and system verification process for large, complex semiconductors, today unwrapped its…
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Companies Rally RISC-V Support for AI and HPC Applications
As RISC-V gains traction as an open-source alternative to Arm, several companies have announced partnerships and research to bolster the ISA. Forecasts show that AI will continue to fuel RISC-V…
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[VIDEO] M1: RISC-V Overview | The Ultimate Guide to RISC-V Architecture
Welcome to the Ultimate Guide to RISC-V Architecture. In this course, our Founder and CEO, Mr. P R Sivakumar, explains the layered architecture of RISC-V open ISA and how we…
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Follow the Leader – Synopsys Provides Broad Support for Processor Ecosystems
Synopsys has expanded its ARC processor portfolio to include a family of RISC-V processors. This was originally reported on SemiWiki last October. There is also a recent in-depth article on the make-up…
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Sipeed Univels the Lichee Book 4A, a Notebook for the “RISC-V Explorer”
Sipeed has announced a new entry in its Lichee RISC-V family, this time putting its high-performance Lichee 4A RISC-V system-on-module into a full-size laptop chassis: the Lichee Book 4A. "Lichee…
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Functional safety static analysis tool for RISC-V
The IAR safety-certified C-STAT tool is now available in the Functional Safety editions of IAR Embedded Workbench for RISC-V, ARM, and Renesas RL78 architectures. The latest IAR Embedded Workbench for…
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A RISC-V World First Independently Developed RISC-V Mainboard for a Framework Laptop from DeepComputing
Today, RISC-V pioneer DeepComputing announced that their first RISC-V Mainboard, compatible with the Framework Laptop 13, is about to be released. Sporting a RISC-V StarFive JH7110 SoC, this groundbreaking Mainboard was…
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[VIDEO] RISC-V Con 2024: “Leveraging RISC-V for hardware software co-design of low power AI accelerators”
Alexander Conklin, Head of Hardware Engineering, Rain AI The compute intensive demands of AI workloads have given rise to a new era in accelerator design. In this talk we’ll take…
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[VIDEO] Banana Pi BPI-F3: Octa Core RISC-V SBC Running Bianbu OS
RISC-V Banana Pi BPI-F3 development board review and specifications, including demonstrations running Bianbu OS from SpaceMIT (who also developed the K1 RISC-V SoC on which this SBC is based). Watch…
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World’s first RISC-V Laptop gets a MASSIVE upgrade and equips with Ubuntu
DeepComputing partners with Canonical to unveil a huge boost to the DC-ROMA RISC-V Laptop family The DC-ROMA RISC-V Laptop II is the world’s first RISC-V laptop pre-installed and powered by…
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[VIDEO] OpenHW Group CORE-V RISC-V open-source cores with CEO Florian ‘Flo’ Wohlrab at Computex 2024 Update
Florian "Flo" Wohlrab, CEO of OpenHW Group, leads a Canadian-based nonprofit that operates globally, focusing on open-source hardware. The organization specializes in creating industrial-grade, fully open-source RISC-V cores that are…
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Lauterbach presents leading debug solutions at the RISC-V Summit in Munich
Hoehenkirchen, Germany - June 13, 2024 - Under the headline "RISC-V Debugging made Easy", Lauterbach, the leading supplier of RISC-V debug and trace tools, will demonstrate at the RISC-V Summit…
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World’s first RISC-V Laptop gets a MASSIVE upgrade and equips with Ubuntu
DeepComputing partners with Canonical to unveil a huge boost to the DC-ROMA RISC-V Laptop family The DC-ROMA RISC-V Laptop II is the world’s first RISC-V laptop pre-installed and powered by…
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Axiomise Heads to RISC-V Summit Europe June 25-27 in Munich
LONDON, June 13, 2024 (GLOBE NEWSWIRE) -- Axiomise, a company noted for enabling formal verification adoption, is headed to the RISC-V Summit Europe to demonstrate formalISA, its automated formal RISC-V…
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Codasip introduces best-in-class RISC-V core for power-efficient applications
Munich, Germany, June 4, 2024 – Codasip, the leader in RISC-V Custom Compute, has introduced a new low-power embedded processor core, and the next generation of processor design automation toolset…
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[VIDEO] ANDES RISC-V CON Silicon Valley 2024
ANDES had their RISC-V Con in Silicon Valley on June 11th. No worries if you weren't able to make it, watch the full conference to learn more! Watch the full…
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Arteris Selected by Esperanto Technologies to Integrate RISC-V Processors for High-Performance AI and Machine Learning Solutions
CAMPBELL, Calif. – June 11, 2024 – Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced that Esperanto Technologies™, a leading developer…
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[VIDEO] Progress in Standardizing Cryptography Extensions for RISC-V Processors
This panel will discuss the state of standardized cryptographic instruction set extensions for RISC-V processors. Lightweight instructions for scalar CPUs, high-performance instructions for vector CPUs, an entropy source interface, and…
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First 32-bit low-power MCU with in-house RISC-V CPU core
Mouser now stocks the R9A02G021 low-power MCUs from Renesas Electronics. Empowering engineers with a multipurpose platform for creating power-efficient, cost-effective applications using an open-source ISA, the R9A02G021 is the company's…
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SpacemiT Muse Pi is a single-board PC with SpacemiT M1 8-core RISC-V processor
Earlier this year Chinese chip maker SpacemiT announced plans to launch several new products powered by the company’s RISC-V processors, including the SpacemiT Muse Book laptop, Muse Box mini PC,…
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Andes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose Hotel
San Jose, CA — Jun 6, 2024 — Andes Technology (TWSE: 6533), the leading vendor in high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International,…
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Getting started with RISC-V! | Soham Kulkarni | MumbaiFOSS 2024
Soham shares his knowledge about RISC-V at the MumbaiFOSS 2024 Conference! Watch the full video here.
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Navigating the RISC-V landscape: unveiling the Embeetle IDE
Embeetle was founded by three engineers with unique insights into embedded software IDEs. The Embeetle team is committed to building a healthy MCU ecosystem, offering convenience to manufacturers and developers.…
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Calligo Technologies Unveils Revolutionary World’s First Posit-enabled RISC-V CPU for General Purpose Computing
BENGALURU, India, June 3, 2024 /PRNewswire/ -- Calligo Technologies Pvt Ltd, a pioneering tech firm based in Bengaluru, India, proudly announces the world's first 8-core Posit-enabled RISC-V CPU – TUNGA, in…
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Rain AI Unveils Andes Technology as Its RISC-V Partner
San Francisco, CA , June 03, 2024 (GLOBE NEWSWIRE) -- Rain AI Licenses Andes AX45MPV and Taps Andes Custom Computing BU to Accelerate Its Launch of Groundbreaking Compute-In-Memory (CIM) Generative…
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Andes Technology announces new SoC and development board
Andes Technology, a supplier of 32/64-bit RISC-V processor cores, has unveiled the QiLai SoC and the Voyager development board to help accelerate the development and porting of large RISC-V applications.…
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Andes Technology Announced the QiLai SoC and the Voyager Development Board
May 30, 2024 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International,…
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Building a DIY 256-Core RISC-V computer
If you’re interested in building your very own 256-Core RISC-V supercomputer, you might find this project video intriguing. It details the ambitious method of creating a 256-core RISC-V supercomputer using…
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[VIDEO] The Magic of RISC-V Vector Processing
The 1.0 RISC-V Vector Specification is now Ratified, and the first pieces of silicon using the new spec are starting to hit the shelves. I go over the utility of…
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Exciting Announcements: Unveiling the Agenda for the 2024 RT-Thread Global Tech Conference!
RT-Thread IoT OS is thrilled to unveil the agenda for the highly anticipated 2024 RT-Thread Global Tech Conference (RGTC). This year’s event promises to be a remarkable gathering of industry…
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World’s first RISC-V multi-mode LTE chipset for 450MHz
GCT Semiconductor has developed the first multi-mode LTE chipset for the 450MHz spectrum, using two RISC-V cores. The GDM7243SL developed by GCT is the world’s first highly integrated multi-mode LTE…
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Canonical releases Ubuntu 24.04 Server image for Milk-V Mars RISC-V SBC
Canonical has been releasing Ubuntu RISC-V images for SBCs and QEMU at least since 2021. The latest addition is an Ubuntu 24.04 Server image for the Mars credit-card-size SBC powered…
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Canonical enables Ubuntu on Milk-V Mars, a credit-card-sized RISC-V SBC
May 28th, 2024 – Canonical announced that the optimised Ubuntu 24.04 image is available for Milk-V Mars, the first credit-card-sized high-performance RISC-V Single Board Computer (SBC) delivered by Shenzhen MilkV Technology Co., Ltd.…
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SEALSQ RISC-V Chips Adoption is Predicted to Get AI Boost Making it a Viable Competitor to Traditional GPUs
RISC-V technology is revolutionizing the microchip industry, challenging established giants and paving the way for transformative changes. By the end of 2022, the industry had already embraced over 10 billion…
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[VIDEO] FSCK 2024 – RISC-V – The Only Architecture You’ll Ever Need
RISC-V – never heard of it? The open-source processor architecture is relatively new, but already making big waves as the ISA for all sorts of applications. In this talk media.ccc.de…
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[VIDEO] Master RISC-V Processors with Bluespec for Achronix FPGAs | Complete Guide & Insights
Dive into the world of RISC-V processors with Loren Hobbs, VP of Product and Business Development at Bluespec, an Achronix partner. This detailed presentation will equip you with essential knowledge…
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Andes Technology and Arteris Partner To Accelerate RISC-V SoC Adoption
Highlights: – Andes Technology and Arteris partnership aims to support the growing adoption of RISC-V SoCs by mutual customers. – Focus is on high-performance/low-power RISC-V-based designs across a wide range…
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Edge AI to help RISC-V to take 25% of processor market
AI and automotive applications will help the RISC-V open-standard instruction set architecture (ISA) take nearly 25 percent of the processor market by 2030, according to Omdia. The market analyst predicts…
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[VIDEO] How to bring up SYSGO’s PikeOS on a PolarFire® RISC-V SoC | SYSGO & Microchip
The global RISC-V ecosystem is growing rapidly, particularly in the U.S. and China, and consists of nearly four thousand members. This provides a wide choice of technology partners and ensures…
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RISC-V adoption predicted to get AI boost — forecast shows 50% growth every year until 2030 for the open-standard ISA
RISC-V chips are set to become a global powerhouse in the 2020s, with a market share of almost 25% by 2030, according to research by Omdia. The forecast outpaces even RISC-V…
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Andes, HiRain, and HPMicro Join Hands to Build RISC-V AUTOSAR Software Ecosystem
May 14, 2024 —Andes, HiRain, and HPMicro jointly announced that the three parties will cooperate to combine the AndesCoreTM RISC-V processor series, the HPMicro HPM6200 full line of products, and the HiRain…
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RISC-V adoption will be accelerated by AI, according to new Omdia research
LONDON, May 16, 2024 /PRNewswire/ -- RISC-V processors will account for almost a quarter of the global market by 2030, according to new research by Omdia. The open-standard instruction set architecture (ISA) is predicted to experience…
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Global and China Automotive RISC-V Chips Research Report 2024: Market Gains Momentum as Industry Trends Toward Customization and High-Performance Applications – ResearchAndMarkets.com
DUBLIN--(BUSINESS WIRE)--The "Global and China Automotive RISC-V Chip Industry Research Report, 2024" report has been added to ResearchAndMarkets.com's offering. The automotive industry is witnessing a significant shift towards the adoption of RISC-V chips, as…
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Esperanto Technologies and Rapidus Partner to Enable More Energy-Efficient Designs for the Coming “Post GPU Era”
MOUNTAIN VIEW, Calif., May 15, 2024 – Esperanto Technologies™, the leading developer of high-performance, energy-efficient artificial intelligence (AI) and high-performance computing (HPC) solutions based on the RISC-V instruction set, today announced…
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Benchmarking The First RISC-V Cloud Server: Scaleway EM-RV1 Performance
Scaleway by way of their Scaleway Labs group recently launched the Elastic Metal RV1 (EM-RV1) as the world's first RISC-V servers available in the cloud. These RISC-V cloud servers are…
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New Automotive Grade Linux Platform Release Adds Cloud-Native Functionality, RISC-V Architecture and Flutter-Based Applications
AGL’s latest UCB release advances SDV development and takes a software-first approach with support for AWS Graviton and Toyota Embedded Flutter Automotive Grade Linux (AGL), a collaborative cross-industry effort developing an…
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Frontgrade Gaisler Leads the Way in RISC-V Processor Development for Space Applications
GOTHENBURG, Sweden--(BUSINESS WIRE)--Under a contract with the European Space Agency (ESA), Frontgrade Gaisler is designing a new RISC-V processor tailored to meet the requirements of microcontrollers for the space industry.…
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Custom RISC-V cores for GPS augmentation
MerlinTPS is to use a RISC-V processor core from Bluespec for satellite navigation augmentation and backup technology. The deal marks the start of the next phase of MerlinTPS’ next-generation platform…
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Mindgrove Brings First Indigenously-Designed RISC-V MCU to India
The new RISC-V-based SoC is the first microprocessor owned, designed, and marketed entirely from India to the open market. While semiconductor technology is a matter of national security for almost…
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New Automotive Grade Linux Platform Release Adds Cloud-Native Functionality, RISC-V Architecture and Flutter-Based Applications
SAN FRANCISCO, May 9, 2024 /PRNewswire/ -- Automotive Grade Linux (AGL), a collaborative cross-industry effort developing an open source platform for all Software-Defined Vehicles (SDVs), has announced the latest code release of the AGL…
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The Rise of RISC-V and ISO 26262 Compliance
RISC-V technology is beginning its inroads into automotive electrical/electronic (EE) architecture design. Four major trends are driving this evolution: the surge in electric vehicles (EVs), advances in self-driving technology, the emergence…
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X- Silicon Announces a NEW Low-Power Open-Standard Vulkan-Enabled C-GPU™ – a RISC-V Vector CPU Infused with GPU ISA and AI/ML acceleration in a Single Processor Core
SAN DIEGO, May 1, 2024 /PRNewswire/ -- X-Silicon Inc (XSI), a San Diego-based startup, announced today their new NanoTile open-standard low-power "C-GPU" architecture that infuses GPU acceleration into a RISC-V Vector CPU Core with tightly…
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Radiation-Tolerant RISC-V FPGA for Linux in space
Microchip Technology has launched a radiation tolerant version of its PolarFire FPGA with a RISC-V processor sub-system that can run the Linux operating system. The Microchip RT PolarFire system-on-chip (SoC)…
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Cooperation and Competition Behind the Scenes in the RISC-V Community
RISC-V “is changing the way people build every single computer,” says Mark Himelstein, the former CTO at RISC-V International. He joins us to explain the significance of the RISC-V ISA,…
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Here’s why RISC-V is so important
RISC-V has been an industry buzzword over the last few years, making waves with a range of wacky devices and chips from all sorts of manufacturers. This often-hyped technology has sometimes…
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[VIDEO] Applications for the RISC-V Revolution – The Electropages Podcast with Bluespec, Inc
Welcome to another episode of the Electropages podcast. Today, host Robin Mitchell is joined by Charlie Hauck, CEO of Bluespec Inc, to explore the latest developments in RISC-V technology and…
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Compiler toolset for RISC-V in safety and security-critical automotive applications
TASKING has introduced the new compiler toolset VX-Toolset for RISC-V. The industry's first ISO 26262 and ISO/SAE 21434 compliant compiler enables the development of automotive embedded software that fulfills stringent…
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A Striped Bus Architecture for Minimizing Multi-Core Interference
Understanding the intricacies of software timing behaviour is crucial, especially in safety-critical systems and systems with real-time requirements. While analysing timing on single-core processor architecture might seem straightforward, the landscape…
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SYSGO Supports RISC-V with its Embedded Linux ELinOS Version 7.2
SYSGO released its support for RISC-V via its embedded Linux ELinOS version 7.2. The platform fully supports Microchip's PolarFire SoC Icicle. The ratification also sees fixes for the 2038 bug…
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RISC-V: Democratizing Innovation in CPU Design
RISC-V has emerged as a groundbreaking force in the semiconductor industry, fundamentally changing the CPU design and manufacturing landscape. By providing an open standard instruction set architecture (ISA), RISC-V has…
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BSC and Brazil’s Instituto ELDORADO Collaborate to Advance RISC-V Development for HPC and AI
An international collaboration between BSC and Instituto ELDORADO will enable Brazil to develop open-source RISC-V technologies to accelerate research and development in the areas of semiconductors and supercomputing. The primary goal of this project…
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IoT & Embedded Technology Report
Embedded World 2024 proved that the industry is becoming more competitive as rapid innovations emerge across a number of different sectors and elements of the product solution stack. With engineering…
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High Degree of Specification Activity Helps with Further RISC-V Adoption
RISC-V International has succeeded in ratifying 40 new technical specifications relating to the RISC-V instruction set architecture (ISA) over the course of the last 2 years. This means that engineers…
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Unlocking the future of India’s semiconductor landscape with RISC-V Innovation
In recent years, India's semiconductor industry has witnessed remarkable growth and innovation, fueled by a combination of several innovations, strategic partnerships, and technological advancements. At the heart of this revolution…
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Enhancing the RISC-V Ecosystem with S2C Prototyping Solution
RISC-V’s popularity stems from its open-source framework, enabling customization, scalability, and mitigating vendor lock-in. Supported by a robust community, its cost-effectiveness and global adoption make it attractive for hardware innovation…
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Ventana and Canonical collaborate on enabling enterprise data center, high-performance and AI computing on RISC-V
RISC-V, an open standard instruction set architecture (ISA), is rapidly shaping the future of high-performance computing, edge computing, and artificial intelligence. The RISC-V customizable and scalable ISA enables a new…
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embedded world 2024 Best in Show Winners
All entries are judged using a 15-point rubric, that assesses design excellence, relative performance, and market impact/disruption. Judging is managed by the ECD Content Team. Read the full article.
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[VIDEO] RISC-V CEO interview: Calista Redmond talks future of RISC-V markets at Embedded World 2024
Calista Redmond, the CEO of RISC-V International, spoke at Embedded World 2024, highlighting the growth and global presence of RISC-V. With over 2300 members in 70 countries, RISC-V is experiencing…
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RISC-V compiler toolset targets automotive functional safety
TASKING has introduced the industry’s first ISO 26262 and ISO/SAE 21434 compliant compiler toolset, designated VX-Toolset for RISC-V. The compiler facilitates the development of automotive embedded software that meets stringent…
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Imagination Reveals RISC-V Processor at Embedded World 2024
Following up on our previous reporting on the changes at UK-based Imagination Technologies, the company announced a new RISC-V applications processor IP, the Imagination APXM-6200 CPU, at the 2024 Embedded World conference.…
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SiFive Unveils the HiFive Premier P550, the First Commercially Available Out-of-order RISC-V Development Board
HiFive Premier P550 is the highest performance RISC-V development board on the market, offering developers unmatched flexibility and performance Nuremberg, Germany – April 9, 2024 – Today at Embedded World, SiFive,…
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Imagination’s new Catapult CPU is driving RISC-V device adoption
Imagination Technologies today unveils the next product in the Catapult CPU IP range, the Imagination APXM-6200 CPU: a RISC-V application processor with compelling performance density, seamless security and the artificial intelligence capabilities needed to…
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IAR, Nuclei, and MachineWare Join Forces To Speed Up Innovation in RISC-V ASIL Compliant Automotive Solution
Uppsala, Sweden, April 8, 2024 - IAR, the leader in software solutions and services for embedded development, has joined forces with Nuclei System Technology and MachineWare to accelerate innovation in…
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Imagination’s New Catapult CPU Is Driving RISC-V Device Adoption
LONDON--(BUSINESS WIRE)--Imagination Technologies today unveils the next product in the Catapult CPU IP range, the Imagination APXM-6200 CPU: a RISC-V application processor with compelling performance density, seamless security and the…
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RISC-V Cryptography Evolution: High Assurance and Post-Quantum Cryptography (RWC 2024)
NAME is a talk presented by Markku-Juhani O. Saarinen at RWC 2024. This was the first talk in a session on post-quantum implementations, chaired by Thomas Prest. Watch the full…
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[VIDEO] RISC-V 2024 Update: RISE, AI Accelerators & More
RISC-V annual update, covering developments in RISC-V hardware and software including RISE, Quintaris, and AI accelerators. Watch the full video.
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Semidynamics launches AI IP based on single ISA and one toolchain
Semidynamics has announced an all-in-one unified IP solution that combines RISC-V, vector, tensor and its own Gazzillion technology to enable implementation of AI workloads using just one instruction set and…
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RISC-V International details recent ratifications
Ahead of Embedded World next week, RISC-V International has highlighted 40 technical specifications it has ratified in the past two years covering the key areas of efficiency, vector and virtualization.…
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RISC-V International Reaches Ratification Milestone
ZURICH – April 4, 2024 – RISC-V International, the global standards organization, today announced that 40 new technical specifications have been ratified in the past two years, adding to an extensive list of…
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MIPS Expands RISC-V Ecosystem Support to Enable Early Software Development for Multi-threaded Cores
SAN JOSE, CA – April 04, 2024 – MIPS, a leading developer of efficient and configurable IP compute cores, today announced that it has expanded its collaboration with Synopsys, Inc. to accelerate ecosystem enablement…
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YuzukiHD’s Eight-Core Avaota-A1 Includes a 2 TOPS NPU, RISC-V “Remote CPU,” and Connectivity Aplenty
Embedded hardware specialist YuzukiHD is preparing to launch a single-board computer built around the Allwinner T/A527 system-on-chip (SoC) and boating a RISC-V "remote CPU" and two tera-operations per second (TOPS)…
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[VIDEO] Why Does Formal Verification Matter for Semiconductors?
Axiomise formal verification is about making formal verification normal by deploying consulting and services on customer projects, leveraged by Axiomise training and formalISA for RISC-V. The Axiomise team explains why…
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[VIDEO] From Specs to Verilog: AI assisted logic design on a RISC-V implementation
This session will focus on a demonstration using the RISC-V specification incorporated into a Sinfonia project. Sinfonia utilizes it’s ingested knowledge of RISC-V and the enriched understanding from the LLM…
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Signaloid C0-microSD A compact yet powerful FPGA development board in a microSD form factor
Signaloid C0-microSD is an FPGA development board based on the popular iCE40 FPGA from Lattice Semiconductor in a microSD form factor. You can use it to prototype your designs on a…
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IAR sets the standard with class-leading support for Renesas’ first general-purpose RISC-V MCUs
Uppsala, Sweden, March 27, 2024 - IAR, the leader in software solutions and services for embedded development, is proud to announce enhancements to its premier development environment to support the…
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RISC-V SSD controller provides 14GB/s transfers without a cooling solution
A hot potato: Many PCIe 5.0 SSDs currently on sale provide extremely high transfer rates compared to previous generations, however they all appear to require an often-cumbersome cooling solution to avoid…
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RISC-V PCIe 5 SSD controller for the rest of us hits 14GB/s
A demo of Yingren Technology's YRS820 PCIe 5.0 SSD controller – built entirely on the RISC-V architecture – showed it reading at 14GB/sec and writing at 12GB/sec, without any active…
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RISC-V Unleashes Your Imagination
Since October 2020, Renesas has been officially active in the RISC-V microcontroller space and successfully launched two ASSP products, for motor control and voice-driven HMI systems. Now a general-purpose MCU…
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[VIDEO] Open source lightweight interpreter made in a day
"I redesigned my mini game to use the new CH32X035 chip. It supports full speed USB mass storage now, got an LDR for new features and runs an interpreter that…
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Achronix FPGAs Add Support for Bluespec’s Linux-capable RISC-V Soft Processors to Enable Scalable Processing
SANTA CLARA, Calif. & FRAMINGHAM, Mass.--(BUSINESS WIRE)--Achronix Semiconductor Corporation, a leader in high-performance FPGAs and embedded FPGA (eFPGA) IP, and Bluespec, Inc., an industry leader in RISC-V tools and silicon…
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Renesas Introduces Industry’s First General-Purpose 32-bit RISC-V MCUs with Internally Developed CPU Core
TOKYO, Japan ― Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, today announced the industry’s first general-purpose 32-bit RISC-V-based microcontrollers (MCUs) built with an internally developed CPU core.…
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Podcast EP212: A View of the RISC-V Landscape with Synopsys’ Matt Gutierrez
Dan is joined by Matt Gutierrez. Matt joined Synopsys in 2000 and is currently Sr. Director of Marketing for Processor & Security IP and Tools. His current responsibilities include the…
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Andes Technology: Pioneering the Future of RISC-V CPU IP
On September 13, 2021, Andes Technology Corporation successfully issued its GDR (Global Depositary Receipt) public offering on the Luxembourg Stock Exchange. At the time it made Andes the only international public RISC-V…
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Quad core RISC-V FPGA is automotive qualified
Efinix in California has launched a line of FPGA devices with 32bit RISC-V cores specifically for the automotive industry. The Titanium Ti375 is automotive qualified and with the Efinix Efinity tool…
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Tenstorrent and MosChip Partner on High Performant RISC-V Design
SANTA CLARA, Calif., March 13, 2024 /PRNewswire/ --Tenstorrent and MosChip Technologies announced today that they are partnering on design for Tenstorrent's cutting-edge RISC-V solutions. In selecting MosChip Technologies, Tenstorrent stands to strongly…
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MIPS Expands Global Footprint with New Design Center and Talent for Systems Architects and AI Compute
SAN JOSE, Calif.--(BUSINESS WIRE)--MIPS, a leading developer of efficient and configurable compute cores, today announced the company’s global expansion with the launch of a new R&D center in Austin, TX,…
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StarFive’s RISC-V Based JH-7110 Intelligent Vision Processing Platform Adopted VeriSilicon’s Display Processor IP
SHANGHAI--(BUSINESS WIRE)--VeriSilicon (688521.SH) today announced the successful integration of its Display Processor IP DC8200 into StarFive’s JH-7110 RISC-V mass production SoC. With high performance, low power consumption and high security…
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A custom RISC-V vector instruction to accelerate structured-sparse matrix multiplications
A novel AI-acceleration paper presents a method to optimize sparse matrix multiplication for machine learning models, particularly focusing on structured sparsity. Structured sparsity involves a predefined pattern of zero values in the…
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[VIDEO] BeagleV-Fire Out of Box Experience | RISC-V & FPGA | Microchip PolarFire | BeagleBoard.org
Watch the full video.
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Global and China Automotive RISC-V Chip Industry Research Report 2024: Customized Chips May Become the Future Trend, and RISC-V will Challenge ARM
DUBLIN, March 14, 2024 /PRNewswire/ -- The "Automotive RISC-V Chip Industry Research Report, 2024" report has been added to ResearchAndMarkets.com's offering. Read the full release.
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Canaan’s RISC-V based edge AIoT SoC adopted VeriSilicon’s ISP and GPU IPs
SHANGHAI--(BUSINESS WIRE)--VeriSilicon (688521.SH) today announced the integration of its Image Signal Processor (ISP) IP ISP8000, DeWarp Processor IP DW200, and 2.5D Graphics Processor Unit (GPU) IP GCNanoV into Canaan’s K230…
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Tenstorrent and MosChip Partner on High Performant RISC-V Design
SANTA CLARA, Calif., March 13, 2024 /PRNewswire/ --Tenstorrent and MosChip Technologies announced today that they are partnering on design for Tenstorrent's cutting-edge RISC-V solutions. In selecting MosChip Technologies, Tenstorrent stands to strongly…
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embedded world 2024: Codasip demonstrates CHERI memory protection
Munich, Germany, 13 March 2024 –Codasip, the leader in RISC-V Custom Compute, will demonstrate CHERI memory protection and HW/SW co-optimization at next month’s embedded world 2024 in Nuremberg, Germany. The…
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People to Watch 2024 – Calista Redmond
Congratulations on your selection as a 2024 HPCwire Person to Watch. As a longtime electronics industry executive and the former president of the member-driven OpenPOWER organization, could you tell us…
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Andes Technology: Cultivating Academic Collaboration for Over a Decade with Sustainable Spirit
【Mar. 12, 2024 -Hsinchu, Taiwan】Andes Technology (TWSE: 6533), since the first agreement signed with National Chiao Tung University in 2010, has actively keeping engaged in industry-academia collaboration. Collaborating with universities…
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What is RISC-V and Why Has it Become Important for Java?
RISC stands for reduced instruction set computer, and V points to its fifth release in 2015. RISC-V is the new processor architecture to watch out for. Arm-based processors, which stayed among…
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Tiempo Secure announces TESIC RISC-V Secure Element IP and development kit
Grenoble, France – March 8, 2023 – As security is increasingly the central issue of any SoC (System on Chip) development, for example taking into account initiatives like the Cyber Resilience…
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Here’s Your Sneak Peek at SNUG Silicon Valley 2024
Are you ready to step inside one of the premier conferences in the electronics industry? SNUG Silicon Valley 2024 will be back at the Santa Clara Convention Center in March,…
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Next Euro HPC Chip Coming Next Year Will Be in 2026 EU Exascale System
The next supercomputing chip for Europe’s homegrown Exascale supercomputer will come next year, according to an updated product roadmap. The 2025-bound Rhea-2 chip will succeed the Rhea-1 chip, the ARM-based…
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[VIDEO] RISC-V for Edge AI Applications
Paul Schell, Industry Analyst at ABI Research, discusses the growing start-up and legacy chipset vendor activity around RISC-V processors addressing AI workloads at the edge and highlights how this trend…
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From vision to reality in RISC-V: Interview with Karel Masarik
Karel Masarik is the founder of Codasip and since January 2024 also a member of the board of RISC-V International. Recently, EY named Karel Masarik the regional Entrepreneur of the year…
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How the RISC-V ISA Offers Greater Design Freedom and Flexibility
The need for more flexible and scalable processor architectures in the semiconductor industry continues to rise, contributing to the steady growth in the adoption of RISC-V. Originally developed at the…
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Understanding RISC-V: The Open Standard Instruction Set Architecture
Introduction to RISC-V RISC-V (pronounced as risk five) is an open standard Instruction Set Architecture (ISA) based on Reduced Instruction Set Computing (RISC) computer architecture. Unlike proprietary ISAs, RISC-V is…
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[VIDEO] HAPS high-performance RISC-V prototyping with asynchronous clocks | Synopsys
This video demonstrates high performance and asynchronous clocking using HAPS®-100 and HAPS ProtoCompiler software. The design uses a RISC-V Rocket System integrated highspeed DDR 4, and Synopsys DW PCIE Gen…
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Free tool enables customers to fully configure RISC-V cores
Semidynamics has released its new tool called ‘Configurator’ that puts the power of Semidynamics’ full customisation of a RISC-V processor core in the hands of the customer. The Configurator uses…
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[VIDEO] SBT C Suite Spotlight: Calista Redmond, CEO of RISC V International – Full Conversation
In this installment of SBT's C-Suite Spotlight, President Justin Kinsey has a conversation with CEO of RISC-V International, Calista Redmond. Calista's early career was focused on creating startups, which gave…
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VeriSilicon’s industry-leading embedded GPU IP powers HPMicro’s high-performance HPM6800 series RISC-V MCU
SHANGHAI--(BUSINESS WIRE)--VeriSilicon (688521.SH) today announced that HPMicro’s HPM6800 series, a new generation digital dashboard display and human-machine interface system application platform has adopted VeriSilicon’s high-performance 2.5D Graphics Processor Unit (GPU)…
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Imsys develops RISC-V core, looks to AI in space
Imsys in Sweden has developed a RISC-V processor core and is part of a project to develop an AI accelerator in space. Imsys points to a general EU strategy to…
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Scaleway launches its RISC-V servers in the cloud, a world first and a firm commitment to technological independence
Paris, France - Thursday, February 29, 2024 - Scaleway, the European cloud provider, is proud to launch a range of RISC-V servers, marking once again its commitment to innovation and its…
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1.8 Billion Heterogenous AI Chipsets by 2030, 129 Million RISC-V AI Shipments by 2030 and 36 Other Transformative Technology Stats You Need to Know
The technology community – both innovators and implementers – is at a critical juncture in 2024. Global market pressures are starting to ease, but persistent geopolitical threats are hindering progress.…
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Andes and MachineWare Collaborate on Early RISC-V Software Development for AndesCore™ AX45MPV
Aachen, Germany and Hsinchu, Taiwan, February 27th 2024 MachineWare GmbH and Andes Technology (TWSE:6533), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International…
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Tenstorrent Scores Big Design Win With Japan’s LTSC To Enable Leading-Edge 2nm AI Accelerator
Japan’s Leading-edge Semiconductor Technology Center, or LSTC, was established in late 2022 and is tasked with advancing the country’s research and innovation in areas such as nanotechnology, chip manufacturing, semiconductor…
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[PODCAST] Leading the RISC-V Revolution, SiFive Aims to Take the Computing Industry Throne
SiFive is helping lead the RISC-V revolution in automotive, Android, and AI. Senior VP Jack Kang joins the Moore’s Lobby podcast to provide his insights on the success of SiFive…
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Tenstorrent RISC-V and Chiplet Technology Selected to Build the Future of AI in Japan
SANTA CLARA, Calif., Feb. 27, 2024 /PRNewswire/ -- Tenstorrent is pleased to announce a multi-tiered partnership deal with Japan's Leading-edge Semiconductor Technology Center (LSTC), which selected Tenstorrent's world-class RISC-V and Chiplet IP for its…
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Ashling’s RiscFree™ SDK Toolchain now available with support for MIPS RISC-V ISA compatible P8700 and I8500 CPUs
Feb 23, 2023 SILICON VALLEY, CA, USA. Ashling and MIPS announced today that Ashling’s RiscFree SDK is now available with full support for MIPS RISC-V ISA based CPUs including the…
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Andes Technology and MetaSilicon Collaborate to Build the World’s First Automotive-Grade CMOS Image Sensor Product Using RISC-V IP SoC
Feb 22, 2024 — RISC-V IP vendor Andes Technology and edge computing chip provider MetaSilicon jointly announced that the MetaSilicon MAT Series is the world’s first automotive-grade CMOS image sensor series using…
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Andes Technology and MetaSilicon Collaborate to Build the World’s First Automotive-Grade CMOS Image Sensor Product Using RISC-V IP SoC
Feb 22, 2024 — RISC-V IP vendor Andes Technology and edge computing chip provider MetaSilicon jointly announced that the MetaSilicon MAT Series is the world’s first automotive-grade CMOS image sensor series using…
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Dr Tadej Murovič, Codasip | RISC-V and Codasip Revolutionizing the Future of Processor Design
Dr Tadej Murovič of Codasip discussed how RISC V and Codasip are revolutionizing the future of processor design. Watch the full video.
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BeagleV-Fire Unboxing – Running Linux 6.1 Kernel on RISC-V!
Platima Tinkers on YouTube reviewed the BeagleV-Fire. Watch the full video.
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2024 Outlook With Laura Long of Axiomise
Axiomise pioneered the adoption of formal verification in the semiconductor industry since 2017. Led by visionary CEO, Dr. Ashish Darbari, who has 63 patents in formal verification, and Neil Dunlop an…
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RISC-V Is Inevitable and Reshaping the Future of Compute | Andy Moore
Andy Moore, Senior Marketing Manager of RISC-V International discussed how RISC-V is shaping the future of compute at State of Open Con 2024. Watch the full video.
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RISC-V Processors Addressing Edge AI Devices To Reach 129 Million Shipments by 2030
LONDON, Feb. 14, 2024 /PRNewswire/ -- Reduced Instruction Set Computing (RISC)-V processor architectures are starting to address edge Artificial Intelligence (AI) workloads, and this trend is set to continue throughout…
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Red Hat and RISC-V: To the far edge and beyond
Red Hat has always been an advocate of growth at the intersection of open source and computing solutions–which is exactly where RISC-V can be found. RISC-V is one of those…
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【Andes Webinar】Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series
Speaker: Samuel Chiang , Andes Deputy Director Of Marketing Abstract: In this unique webinar, we take a look at the overview of the latest AndesCore™ RISC-V processor IP lineup. The…
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Effectively hiding sensitive data with RISC-V Zk and custom instructions
Cryptographic hash functions play a critical role in computer security providing a one-way transformation of sensitive data. Many information-security applications benefit from using hash functions, specifically digital signatures, message authentication codes, and…
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Navigating the RISC-V Revolution in Europe
IP collaborations helped propel RISC-V-based innovation in Europe last year, targeting processing speeds that meet the growing performance requirements of artificial intelligence and machine learning applications. The ability of RISC-V…
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Catching up with MEEP: Bringing forward the development of tomorrow’s European exascale supercomputing
The EU-funded MEEP project introduced a large-scale field programmable gate array (FPGA) system involving a complete collection of hardware intellectual properties (IPs) and software components. These were seamlessly integrated into…
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Banana Pi BPI-F3 is a single-board PC with an 8-core RISC-V processor, dual Ethernet and PCIe 2.1
Most of Banana Pi’s single-board computers are powered by ARM-based processors. But the upcoming Banana Pi BPI-F3 has a RISC-V processor instead. The company says the SpacemiT RISC-V K1 processor selected for this board…
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Klepsydra AI and Frontgrade Gaisler Collaborate to Expand Microprocessing Versatility in Space Missions Through AI
Zurich, 17 January 2024 – Klepsydra AI, a leading provider of artificial intelligence (AI) software solutions, and Frontgrade Gaisler, a world leader in embedded computer systems for harsh environments, have announced…
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Ashling announces Ashling’s RiscFree™ C/C++ SDK support for Codasip’s RISC-V-based L31 Core
January-30, 2024, Limerick, Ireland. Embedded tools developer Ashling today announced support for the L31 low-power RISC-V processor core from Codasip in Ashling’s RiscFree software development kit (SDK) and Opella-XD Debug…
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Codasip achieves certification for automotive functional safety and cybersecurity
Munich, Germany, 1 February 2024 – Codasip®, the leader in RISC-V Custom Compute, announced today that it has achieved certification for the functional safety standard ISO 26262 as well as…
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RISC-V Based Architecture Integrates Complex Memory Tasks to Processor
Processor Akurra, modifies the standard RISC-V architecture and instruction set to support their memory allocation technology. VyperCore, a UK-based startup located in Bristol, has achieved a significant milestone in the…
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BellSoft releases Liberica JDK 21 for RISC-V with support
SAN JOSE, Calif., Jan. 30, 2024 /PRNewswire/ -- RISC-V is a free, open RISC instruction set architecture (ISA) that is currently gaining popularity due to its high performance, flexibility, and cost-efficiency. RISC-V advantages are…
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RISC-V Open-Source Architecture Redefining The Future Of Computing
RISC-V is revolutionising edge computing and fundamentally reshaping the broader computing landscape by promoting innovation, collaboration, and democratisation. RISC-V, an open-source instruction set architecture (ISA), is emerging as a significant…
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EDACafe Industry Predictions for 2024 – RISC-V
By Mark Himelstein , CTO, RISC-V International Mark Himelstein What are the top five trends for the RISC-V open standard ISA in 2024? This year has been a great one…
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Dutch startup Innatera unveils T1: a game-changing RISC-V neural-type MCU in the edge AI sensor market
Dutch chip startup Innatera has launched the Spiking Neural Processor T1 to target the edge AI sensor market. Read the full article.
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RISC-V Open-Source Architecture Redefining The Future Of Computing
RISC-V is revolutionising edge computing and fundamentally reshaping the broader computing landscape by promoting innovation, collaboration, and democratisation. RISC-V, an open-source instruction set architecture (ISA), is emerging as a significant…
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EDA Back On Investors’ Radar
EDA is transforming from a staid but strategic sector into a hot investment market, fueled by strong earnings and growth, a clamoring for leading-edge and increasingly customized designs across new…
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RISC-V With Linux 6.8 Restores XIP Kernel Support
With Linus Torvalds back to work, merged to mainline on Wednesday were the RISC-V architecture updates for the in-development Linux 6.8 kernel cycle. One of the features for RISC-V with Linux 6.8 is…
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Frontgrade Gaisler and RISC-V’s Space Journey
The last time we spoke with Sandi Habinc, General Manager, and Jan Andersson, Director of Engineering at Frontgrade Gaisler, we were discussing the TRISAT-R CubeSat and Gaisler’s use of RISC-V’s open standard instruction set…
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StarFive RISC-V SoC’s Camera Subsystem Driver Added To Linux 6.8
Sent in last week were all of the media driver updates for Linux 6.8. Arguably most notable is the introduction of the StarFive Camera Subsystem driver as a new image…
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VyperCore shows RTL simulation of RISC-V core, plans hardware
VyperCore in the UK has passed a major development milestone in the development of a new chip architecture starting with RISC-V. Bristol-based VyperCore is developing an architecture to embed functions…
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Debugging complex RISC-V processors
RISC-V processors are quickly becoming mainstream. The open standard means freedom for many developers, but success depends on the development of a support ecosystem around RISC-V. Industry collaboration is making…
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COMPUTE THE MANDELBROT SET WITH A CUSTOM RISC-V CPU
When faced with an FPGA, some people might use it to visualize the Mandelbrot set. Others might use it to make CPUs. But what happens if you combine the two?…
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YorChip, Inc. announces its first Chiplet for Edge AI applications with IP licensed from Semidynamics, the leader in RISC-V IP based in Barcelona
SAN RAMON, CA, 94582 -- January 17, 2024 -- YorChip, Inc. announces its first Chiplet for Edge AI applications with IP licensed from Semidynamics, the leader in RISC-V IP based in…
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Video: Leveraging the RISC-V efficient trace (E-Trace) standard
Understanding program behavior in complex systems is not easy. Understanding the behavior of complete systems is even more challenging. Get non-intrusive, full-speed and system-level visibility with E-Trace. Processor trace gives…
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ONiO looks to kill the IoT battery with RISC-V microcontroller
A Norwegian chip startup is aiming to eliminate the need for batteries in trillions of devices across the Internet of Things (IoT) Kjetil Meisal, CEO of ONiO talks to Nick…
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What is RISC-V and why is it important?
RISC-V, an open-source instruction set architecture (ISA), has been making waves in the world of computer architecture. “RISC-V” stands for Reduced Instruction Set Computing (RISC) and the “V” represents the…
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CES: MIPS CEO Sameer Wasson sees RISC-V as path to freedom
Sameer Wasson is passionate about RISC-V architecture and recently became CEO of MIPS to show the world how important an architecture it is. He uses words like “freedom” when talking…
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SEGGER’s new Embedded Studio: One IDE for both Arm and RISC-V
SEGGER is excited to announce the new Embedded Studio - V8.10. This cutting-edge, multi-platform IDE now also supports multiple architectures with a single setup. The same software can be used to build…
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DFRobot Brings RISC-V and Matter Compatibility to Its FireBeetle 2 Board with New ESP32-C6 Variant
DFRobot has launched a new FireBeetle 2, swapping out the original design's Espressif ESP32-S3 chip for the RISC-V-based ESP32-C6 — which brings with it support for Wi-Fi 6 (IEEE 802.11ax)…
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Andes Introduces RISC-V Out-of-Order Superscalar Multicore Processor
The new CPU features the company’s first out-of-order architecture for higher instruction throughput, better performance, and faster processing speeds. Read the full article.
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BeagleV-Fire Board Blends RISC-V and FPGA
The BeagleBoard family of modules is built around a dual 46-pin BeagleBone cape header. The BeagleV-Fire is the latest platform. In the demo, a BeagleBone cape with interfaces is used…
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China researchers report 256 core, chiplet-based processor
The China Academy of Sciences has reported on a chiplet-based architecture of “Big Chip” as a means of exploring the challenges and options for scaling processor performance. The research team…
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Andes Technology and Spacetouch Collaborate to Unveil High-Tech Edge-Side AI Audio Processor Featuring the Powerful RISC-V AndesCore™ D25F
Hsinchu, Taiwan, Jan. 08, 2024 (GLOBE NEWSWIRE) -- Andes Technology (TWSE: 6533), a leading supplier of 32/64-bit, high-performance and low-power RISC-V processor cores and a Founding Premier member of the…
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The SHD Group Has Released a Complimentary Version of the 2024 RISC-V Market Analysis Report Containing Current Market Data and Future Projections
SAN JOSE, Calif., January 8, 2024 (Newswire.com) - The SHD Group, a leading trade analyst and business development firm, today announced the release of a free version of the 2024 RISC-V…
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Andes Announces General Availability of the New RISC-V Out-Of-Order Superscalar Multicore Processor, the AndesCore™ AX65
Hsinchu, Taiwan, Jan. 04, 2024 (GLOBE NEWSWIRE) -- Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today proudly…
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WCH RISC-V microcontrollers can now be programmed with the Arduino IDE
WCH has launched some interesting RISC-V microcontrollers in the last year or so, including the “10 cents” CH32V003 RISC-V microcontroller with 2KB SRAM and 16KB flash or the CH32V307with more resources (up to…
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Five Leading Semiconductor Industry Players Incorporate New Company, Quintauris, to Drive RISC-V Ecosystem Forward
MUNICH--(BUSINESS WIRE)--Semiconductor industry players Robert Bosch GmbH, Infineon Technologies AG, Nordic Semiconductor ASA, NXP® Semiconductors, and Qualcomm Technologies, Inc., have formally established Quintauris GmbH. Headquartered in Munich, Germany, the company…
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Adding Physical Memory Protection to the VeeR EL2 RISC-V Core
Antmicro’s work with CHIPS Alliance’s Caliptra Root of Trust project, led by Google, AMD, NVIDIA, and Microsoft focuses around providing automated testing and verification infrastructure including code quality checks, code indexing, coverage and…
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[VIDEO] Synopsys ARC-V RISC-V Processor IP | Synopsys
Synopsys ARC-V Processor IP delivers the optimal power-performance-efficiency and extensibility of ARC processors with broad software and tools support from Synopsys and the expanding RISC-V ecosystem. Watch Now.
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RISC-V hardware ecosystem gets strong industry support – Qualcomm joins with four other industry players to form Quintauris
Qualcomm and four other significant semiconductor firms have officially joined forces to establish Quintauris, a company focused on developing "next-generation hardware" based on the RISC-V open-standard architecture (via Business Wire). The…
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World’s first RISC-V handheld gaming system announced — retro gaming platform uses Linux
RISC-V-based processors have been making inroads into a wide range of applications, from tiny microcontrollers to data center processors. However, RISC-V hasn't been used for many consumer or gaming devices (except,…
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RISC-V is Creating a ‘Linux Movement’ in Hardware
In 1991, when Linus Torvalds created Linux, an open-source operating system, it threatened Microsoft’s business as Linux was an alternative to one of its core products-Windows. The open-source nature of…
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RISC-V Summit report: Meta leads the way for custom processors
As a regular attendee of the RISC-V Summit US, I’ve come to appreciate the unique blend of cutting-edge technology discussions and the sunny California weather. Indeed, a welcome departure for…
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RISC-V Summit Buzz – Launchpad Showcase Highlights Smaller Company Innovation
One of the goals of the recent RISC-V Summit was to demonstrate that the RISC-V movement is real – major programs by large organizations committing to development around the RISC-V…
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Open-Source Chip Design Takes Hold in Silicon Valley
A decade-old standard for designing semiconductors called RISC-V is gaining traction as technology companies look at making their own high-performance and specialized chips for artificial intelligence and mobile devices. Read…
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Sameer Wasson’s Vision for MIPS/RISC-V
MIPS today is RISC-V. Unique to MIPS is that it has figured out a recipe, protecting the strengths of MIPS ISA while leveraging RISC-V to extend and differentiate their cores.…
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Sipeed Takes RISC-V Into the Gaming Arena with the Nintendo Switch-Like Lichee Pocket 4A
Embedded hardware specialist Sipeed has unveiled a new carrier for its high-performance Lichee Module 4A (LM4A) RISC-V system-on-module (SOM), and this one's a little unusual: it's the company's answer to…
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BSC presents Sargantana, the first open-source chips designed in Spain
The Barcelona Supercomputing Center – Centro Nacional de Supercomputación (BSC-CNS) presented the new Sargantana chip, the third generation of open source processors designed entirely at the BSC. The development of…
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RISC-V and Arteris: Shaping the Future of Chip Design
Overview RISC-V is revolutionizing the semiconductor world with its promise of freedom to innovate and enable specialization, fueling the golden age of semiconductors. The world craves smarter, more specialized devices.…
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Andes Awards Imperas 2023 Partner of the Year
Oxford United Kingdom, Dec. 12, 2023 (GLOBE NEWSWIRE) -- Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Andes Technology Corporation, a leading supplier of high efficiency, low-power…
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Reviewing the 2023 RISC-V Summit
The 2024 RISC-V Summit is already in the planning stages, but if you missed attending the 2023 version, then you're in luck. The keynote and technical session videos are available. I was…
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[PODCAST] A Tour of the RISC-V Movement and SiFive’s Contributions with Jack Kang
Dan is joined by Jack Kang of SiFive. As a member of the founding team at SiFive, Jack oversees the Business Development, Customer Experience, and Corporate Marketing groups. He is responsible…
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[VIDEO] The RISC-V Revolution
RISC-V is a fast growing CPU architecture. This talk will give you an overview on what is driving the RISC-V eco-system. We will look into RISC-V profiles and extensions and…
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Renesas Champions the RISC-V Cause With Its Own 32-bit RISC-V CPU
Renesas has announced one of the first independently developed 32-bit RISC-V CPUs. Renesas, long a major player in the industrial MCU and CPU universe, has announced the release of a…
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[VIDEO] RISC-V Summit 2023 – Recap from OpenHW Group
Check out our video recap to see how we plan on keeping the momentum going. We look forward to bringing you exciting updates, collaborations, and info on where you can…
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RISC-V’s embedded foray with a 32-bit MCU development
One of the largest vendors of embedded processors has independently developed a CPU core for the 32-bit general-purpose RISC-V market; it can be used as the main CPU or on-chip…
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RISC-V Summit Buzz – Semidynamics Founder and CEO Roger Espasa Introduces Extreme Customization
Founded in 2016 and based in Barcelona, Spain, Semidynamics™ is the only provider of fully customizable RISC-V processor IP. The company delivers high bandwidth, high performance cores with vector units…
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RISC-V to the Core: New Horizons
The increasing popularity of the RISC-V ISA within the semiconductor industry is a boon for innovation. It provides designers with unprecedented flexibility and will slowly but steadily challenge and transform…
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Canonical joins the RISC-V Software Ecosystem (RISE)
Canonical is delighted to announce it is now a member of the RISC-V Software Ecosystem (RISE) to contribute to commercial readiness of open source software for RISC-V. Canonical’s commitment to RISE…
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RISC-V Summit Buzz – Axiomise Accelerates RISC-V Designs with Next Generation formalISA®
If the recent RISC-V Summit proved one thing it’s that open-source hardware design, and particularly the RISC-V instruction set architecture (ISA) has entered the mainstream. It is a design methodology…
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META SEES LITTLE RISK IN RISC-V CUSTOM ACCELERATORS
Many have waited years to hear someone like Prahlad Venkatapuram, Senior Director of Engineering at Meta, say what came out this week at the RISC-V Summit: “We’ve identified that RISC-V…
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Renesas Unveils the First Generation of Own 32-bit RISC-V CPU Core Ahead of Competition
TOKYO, Japan ― Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, announced today that it has designed and tested a 32-bit CPU core based on the open-standard RISC-V…
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IAR Unveils the TCO Calculator: A Breakthrough for Embedded Engineering
Uppsala, Sweden; November 28, 2023 – IAR, the world leader in software and services for embedded development, has launched an innovative tool to transform how companies and decision-makers evaluate development tool…
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Customization? Yes! After tape-out? Yes!
Another RISC-V Summit is behind us. It was a very well-attended event with many exciting talks and companies highlighting their products at the exhibition. One of the main themes was, once again,…
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Hardware-Assisted Verification: Ideal Foundation for RISC-V Adoption
The semiconductor industry has seen RISC-V go from hype to reality, leading us to where we are today. At a time when RISC-V is being used in many vertical markets,…
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AMD’s fastest gaming GPU now works with RISC-V CPUs, AMD Radeon RX 7900 XTX open source Linux drivers available
A little over two years ago an enthusiast managed to make AMD's Radeon RX 6700 XT work on a RISC-V development board under Linux, which was not a particularly easy task.…
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RISC-V Gains Momentum As EDA & AI Chip Design Leader Announces New IP
In recent years, the RISC-V architecture has gained significant traction amongst a wide variety of chipmakers. It may be less than a decade since the first RISC-V workshops were held,…
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RISC-V Rollouts Abound at This Week’s North America RISC-V Summit
As the RISC-V Summit 2023 comes to a close this week, many organizations have announced new innovations and initiatives in the RISC-V community to make the architecture more accessible to new designers. Compared to other…
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[VIDEO] RISC-V Taipei Day: Trends In Ai & Automotive
The AI & automotive industry are both undergoing a major transformation. AI is being used to improve safety, efficiency, and comfort in vehicles, and it is also being used to…
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[VIDEO] 023 RISC-V Taipei Day: Extending RISC-V Intelligence From Cloud To Edge
Equipped with RISC-V's powerful Vector ISA and automated customer extension framework, Andes solutions have been adopted in over a dozen innovated datacenter AI/ML accelerators such as Meta’s MTIA first generation…
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[VIDEO] 2023 RISC-V Taipei Day: Scalable RISC-V For Digital Transformation
The human race is entering an era in which digital technology is profoundly transforming every aspect of human life. Digital transformation refers to the use of digital technologies to revolutionize…
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[VIDEO] 2023 RISC-V Taipei Day: Bridging The Divide – Unifying RISC-V Through Binary Translation
In the ever-evolving landscape of RISC-V ISA, binary translation emerges as a critical enabler for its continuous evolution and innovation, effectively managing the potential fragmentation that accompanies the introduction of…
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[VIDEO] 2023 RISC-V Taipei Day: RISC-V is Leading Technology in the World
RISC-V has stood on par with x86 and ARM, establishing itself as one of the three leading global instruction sets for the coming several decades, making it the preferred choice…
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2023 RISC-V Taipei Day: RISC-V is Inevitable
RISC-V adoption has accelerated across domains, from embedded to enterprise, from automotive to HPC. RISC-V has grown faster than any other architecture in history with both technical and business advantages.…
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Andes Technology Partners with WITTENSTEIN high integrity systems (WHIS) to Build Safety-Critical Solutions with RISC-V Processors
Hsinchu, Taiwan, Nov. 13, 2023 (GLOBE NEWSWIRE) -- Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V…
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Understanding RISC-V: The Open Standard Instruction Set Architecture
With a groundbreaking open-source architecture, RISC-V is paving the way for a new era of computing technology. In this article, we’ll delve into RISC-V’s evolution, its underlying principles and technical…
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Integrating PikeOS With Microchip’s RISC-V Based PolarFire® SoC FPGA
This blog post reviews the RTOS developed by SYSGO GmbH, PikeOS, and the process for building and integrating an embedded system with PikeOS and Microchip's PolarFire® SoC FPGAs. Read the full article.
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[VIDEO] Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
As semiconductor industry leaders, Bosch, Infineon, Nordic Semiconductor, NXP, and Qualcomm collaborate to drive the acceleration of automotive RISC-V semiconductors, join us for an insightful webinar on how you too…
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RISC-V Summit 2023: Embedded Editor Report, Day 2
In a release, Calista Redmond, CEO of RISC-V International, said, “The biggest takeaway for the RISC-V community this year is that we’re going to see RISC-V everywhere. More and more…
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RISC-V: Projected Growth to Over 16 Billion Chips by 2030
The RISC-V open standard instruction set architecture (ISA) has made significant strides since its introduction in August 2014. According to RISC-V International, it has already been incorporated into more than one billion…
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RISC-V Summit 2023: Embedded Editor Report
It’s been a banner day here at the Santa Clara Convention Center for the RISC-V Summit. We’ve been treated to many amazing and optimistic keynotes, including one from Prahlad Venkatapuram,…
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Ventana’s 192-Core RISC-V CPU Takes Aim At AMD Epyc Genoa And Bergamo
The age of full-fledged RISC-V data center CPUs is nearly upon us, as Ventana's 192-core Veryon V2 is coming in 2024 (via ServeTheHome). Ventana, founded in 2018, claims the Veryon V2…
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OpenHW Group Announces CORE-V CVA6 Platform Project for RISC-V Software Development & Testing
SANTA CLARA, Calif.--(BUSINESS WIRE)--Today, at the RISC-V Summit, the OpenHW Group announced the multi-member CORE-V CVA6 Platform project. The platform is an open-source FPGA-based software development and testing environment for RISC-V processors designed…
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New RISC-V processors address demand for open source and performance
This year’s annual RISC-V Summit taking place this week in Santa Clara seemed to have a definite buzz around it. What’s apparent is if you were wondering if the architecture…
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Synopsys Moves To RISC-V To Help SoC Developers
ARC and Arm are both companies that design and license microprocessor (CPU) architectures. ARC processors are known for their customizability and low power consumption, making ARC an ideal choice for…
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RISC-V Summit North America 2023: Best in Show Nominees
Here are the nominees for Best in Show at the 2023 RISC-V Summit North America. Read the full article.
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More Than 16 Billion RISC-V Chips Forecasted by 2030
The RISC-V open standard instruction set architecture (ISA) has come a long way since it was introduced in August 2014, and according to RISC-V International, the architecture has already been…
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Ventana and Imagination Partner to Deliver World’s Highest Performance RISC-V CPU & GPU Solutions
CUPERTINO, Calif. / LONDON – November 7, 2023 – Ventana Micro Systems Inc. and Imagination Technologies today announced a partnership to deliver best-in-class RISC-V SoCs solutions that give customers control over their heterogeneous SoC…
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Ventana Introduces Veyron V2 — World’s Highest Performance Data Center-Class RISC-V Processor and Platform
CUPERTINO, Calif. – November 7, 2023 – Ventana Micro Systems Inc. today announced the second generation of its Veyron family of RISC-V processors. The new Veyron V2 is the highest performance RISC-V…
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Synopsys Expands Its ARC Processor IP Portfolio with New RISC-V Family
SUNNYVALE, Calif., November 7, 2023 /PRNewswire/ – Synopsys, Inc. (Nasdaq: SNPS) today announced it has extended its ARC® Processor IP portfolio to include new RISC-V ARC-V™ Processor IP, enabling customers to choose from a broad range…
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OpenHW Group Announces CORE-V CVA6 Platform Project for RISC-V Software Development & Testing
SANTA CLARA, CALIF., November 7, 2023 – Today, at the RISC-V Summit, the OpenHW Group announced the multi-member CORE-V CVA6 Platform project. The platform is an open-source FPGA-based software development and testing environment…
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BeagleBoard.org Makes FPGA and RISC-V Accessible with New BeagleV-Fire Single Board Computer at $150
BeagleBoard.org, a pioneer in open-source single-board computers (SBCs), is excited to unveil the BeagleV®-Fire, a revolutionary SBC powered by the Microchip’s PolarFire® MPFS025T FCVG484E 5x core RISC-V System on Chip…
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Ashling announce RiscFree™ C/C++ SDK support for the newly launched Synopsys ARC-V RISC-V ISA based Processors
November-7, 2023, RISC-V Summit, Santa Clara, Silicon Valley, California, USA Ashling today announced support for the Synopsys ARC-V RISC-V ISA compliant Processor family. Ashling, as a long-term Synopsys partner for…
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High performance GPU cores for cloud gaming with RISC-V
Imagination Technologies in the UK has launched a line of high-performance GPU IP with support for DirectX for cloud-based streaming gaming systems The IMG DXD includes a hardware-based implementation of DirectX…
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The Rise of RISC-V: From University Lab to Global Force in Silicon Design
RISC-V originated in academia as a summer project and later turned into a global phenomenon driving a new era of innovation in the semiconductor industry. Today, RISC-V is in more than…
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Ubilite Licenses RISC-V Application Processor IP Core from CAST
RISC-V Summit, Santa Clara, California — November 7, 2023 -- Semiconductor intellectual property provider CAST today announced that ultra-low-power Wi-Fi chipset developer Ubilite, Inc. has licensed a RISC-V IP core for…
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Andes and Vector Propel RISC-V AUTOSAR Software Innovations for the Automotive Industry
Hsinchu, Taiwan and Stuttgart, Germany – Nov. 6, 2023 – Andes Technology, the renowned supplier of high-efficiency, low-power 32/64-bit RISC-V processors and a Founding Premier member of RISC-V International, and Vector,…
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What is RISC-V? CTO Mark Himelstein Explains Its Role in Computer Science – The Electropages Podcast
In this very special episode of the Electropages podcast, host Robin Mitchell gets a chance to talk with Mark Himelstein, Chief Technology Officer of RISC-V International, to explore the ground-breaking…
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Tenstorrent and Imperas Set to Provide Model of RISC-V Core
In a recent release, Imperas Software, a RISC-V simulation solutions company, announced that it has teamed up with Tenstorrent, an AI computing company, to make available a model of the Tenstorrent…
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Imperas RISC-V solutions for developers – accelerating RISC-V
Imperas Software has introduced the latest product updates as a general release to all customers and users. These product updates include the latest models of RISC-V processors, ImperasDV processor verification…
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Hyperion Core Joins RISC-V International as a Strategic Member
Düsseldorf, 30 October, 2023 – Hyperion Core Joins RISC-V International as a Strategic Member Hyperion Core, the company that brings affordable AI processing to the end-users, has joined RISC-V International, the…
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Ashling RISC-V Summit Product Announcements
Nov 6th, 2023, RISC-V Summit, Santa Clara, Silicon Valley, California, USA At this year’s RISC-V Summit, we'll showcase our latest tools & solutions for RISC-V, including the following: Our new TraceLLM AI-driven,…
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Qamcom boosts RISC-V beyond the edge with QERV
An increasingly digitalized world requires exploring new ways to add intelligence into everything around us. As RISC-V is redefining computing through a collaborative and inclusive ecosystem that provides value for…
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Sophgo Licenses SiFive RISC‑V Processor Cores to Drive High-Performance AI Computing Innovation
Santa Clara, Calif., November 1, 2023 – Today, Sophgo announced that the company has licensed several SiFive RISC-V high performance processor cores, the SiFive Performance P670 and SiFive Intelligence X280 to develop RISC-V AI computing…
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Imperas RISC-V Solutions for Developers – Accelerating RISC-V
Oxford, United Kingdom, November 1, 2023 — Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced the latest product updates as a general release to all customers and…
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Imperas RISC-V Solutions for Developers – Accelerating RISC-V
Oxford, United Kingdom, November 1, 2023 — Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced the latest product updates as a general release to all customers and…
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RISC-V Is Here! RISC-V Summit North America Showcases Innovation, Products, Boards, Community
RISC-V is here! So is RISC-V Summit North America 2023, which takes place November 6th-8th in Santa Clara, CA. One of our primary goals for the event this year is to showcase…
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Codasip Announces First Commercial Implementation of CHERI Memory Protection
RISC-V is growing rapidly in adoption and attention and leading up to the RISC-V Summit, taking place in Santa Clara November 7 and 8, Codasip has introduced its 700 family of…
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Codasip delivers processor security to actively prevent the most common cyberattacks
Munich, Germany, 31 October 2023 – Codasip, the leader in RISC-V Custom Compute, today announced the first commercial implementation of CHERI, the advanced security mechanism the semiconductor industry needs. Capability…
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[PODCAST] The Growth and Impact of RISC-V and a Peek at the Upcoming RISC-V Summit with Calista Redmond by Daniel Nenni
Dan is joined by Calista Redmond, CEO of RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including vice president of IBM Z Ecosystem where…
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The Road to the RISC-V Summit: Microchip
Microchip is packing up in Chandler, Arizona and will start its trip to the RISC-V Summit in Santa Clara, California, November 7th and 8th, 2023, and November 6 being Member Day. Microchip will be…
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Tenstorrent Teams with Imperas to Provide Model of the Tenstorrent Ascalon RISC-V Core
Oxford, United Kingdom, October 30, 2023 — Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Tenstorrent, a next-generation computing company that builds computers for AI, has collaborated with…
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S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V Processor
S2C announced that the Beijing Institute of Open Source Chip (BOSC) adopted its Prodigy S7-19P Logic System, a VU19P-based FPGA prototyping solution, in the development of the “XiangShan” RISC-V processor.…
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Google will release Android RISC-V emulators to test apps in 2024
Earlier this month, Qualcomm announced it was working with Google on a RISC-V Wear OS chip. The Android team today provided an update on RISC-V adoption, including an initial timeline and emulator support.…
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Hyperion Core Joins RISC-V International as a Strategic Member
Düsseldorf, 30 October, 2023 – Hyperion Core Joins RISC-V International as a Strategic Member Hyperion Core, the company that brings affordable AI processing to the end-users, has joined RISC-V International, the…
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Android and RISC-V: What you need to know to be ready
In December of 2022, Google announced at the RISC-V Summit that they were accepting Android patches for RISC-V. On the Google Open Source Blog, Lars Bergstrom & Greg Simon give…
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CHIPS Alliance Technology Update
Join us for the next Technology Update featuring informative, technical talks on open source hardware collaborative development. Hosted by Google in Sunnyvale, California, the event includes speakers from Google, Antmicro,…
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Top 5 Facts about RISC-V – Tom’s Top Five
RISC-V is an open-source instruction set architecture that can be used to develop custom processors. It's challenging not just Intel and AMD but Arm as well. Here are the top…
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On the EVE of the RISC-V Summit North America
The ESD Alliance hosted an engrossing evening in the early days of RISC-V featuring two of its authors. At the time, RISC-V was a fledgling concept and it’s doubtful anyone…
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Ashling and InCore announce Ashling’s RiscFree™ C/C++ SDK support for InCore’s RISC-V-based Azurite Cores.
October-17, 2023, Chennai, India and Limerick, Ireland. Fabless processor core IP provider InCore Semiconductors and embedded tools developer Ashling today announced support for the Azurite family of RISC-V processor cores…
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Microchip Showcases Expanded RISC-V-Based Solutions, Partnerships and System Design Tools at 2023 RISC-V Summit
CHANDLER, Ariz., October 25, 2023, RISC-V Summit — Designers who create systems for the complex Intelligent Edge need flexible, high-performance hardware and system-software combinations that easily handle demanding workloads while meeting…
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Harnessing the RISC-V Wave: The Future is Now
RISC-V is inevitable - it became the mantra of RISC-V, and it's true. But before we see why that is, let’s step back and discuss what RISC-V is and why…
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First fully coherent RISC-V Tensor unit for AI chip design
SemiDynamics in Spain has developed a RISC-V Tensor Unit for AI chip design based on its fully customisable 64bit cores. The RISC-V Tensor unit is integrated into the cache sub-system,…
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Semidynamics launches first fully-coherent RISC-V Tensor unit to supercharge AI applications
Barcelona, Spain – 24 October, 2023. Semidynamics has just announced a RISC-V Tensor Unit that is designed for ultra-fast AI solutions and is based on its fully customisable 64-bit cores. State-of-the-art…
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Codasip announces next-generation RISC-V processor family for Custom Compute
Introducing the highly flexible 700 family for unlimited innovation Munich, Germany, 17 October 2023 – Codasip, the leader in RISC-V Custom Compute, announced today a new highly configurable family of…
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Research Consortium sets Standards in the Field of Open Source Hardware: Open Tools used for a Security Chip
The security chip (at the middle of the bottom) is built in flip-chip technology on an auxiliary board and plugged into a standard socket on the main board. The main…
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What is RISC-V and how will it redefine your next-gen wearable tech?
When discussing computer hardware, x86, and ARM are household names when discussing microprocessor architecture. They've been around for decades and are still going strong, powering the newest and most powerful CPUs from…
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Andes Technology Unveils Andes D23 and N225 Cores Pioneering the Next Generation of Compact, Performant, and Secure RISC-V Processor Technology
Hsinchu, Taiwan – Oct. 17, 2023 – Andes Technology, the renowned supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, proudly announces the release…
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Qualcomm to Bring RISC-V Based Wearable Platform to Wear OS by Google
Highlights: Qualcomm and Google are extending their collaboration on wearables by developing a RISC-V Snapdragon Wear™ platform that will power next-generation Wear OS solutions. Work has begun and will continue,…
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Qualcomm Adopts RISC-V for Next-Gen Snapdragon Wear Platform
Qualcomm and Google announced that they had agreed to expand their partnership to development of a Snapdragon Wear platform based on the RISC-V instruction set architecture (ISA) designed for next-generation…
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SharpRISCV Overview: A Browser-Based RISC-V Assembler for Seamless Learning and Exploration
In the ever-evolving landscape of computer architecture, RISC-V stands out as an open-source instruction set architecture that offers flexibility and adaptability. To facilitate learning and exploration of RISC-V assembly language,…
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Codasip announces next-generation RISC-V processor family for Custom Compute
Munich, Germany -- October 17, 2023 – Codasip®, the leader in RISC-V Custom Compute, announced today a new highly configurable family of RISC-V baseline processors for unlimited innovation. The family, called…
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Codasip 700 RISC-V processor family: Bringing the world of Custom Compute to everyone
Today, technology innovators must have new ways to create differentiated products. How are they supposed to meet the demand for more computational performance when semiconductor scaling laws are showing their limits?…
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SiFive Rolls Out RISC-V Cores Aimed at Generative AI and ML
SiFive has released two new processors, one to target machine learning applications, and one to target general-purpose HPC. The RISC-V movement is one of the hottest things in the computing…
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SiFive unveils two new high-performance RISC-V processors
SiFive, a RISC-V processor design firm, unveiled two new chip designs aimed at bringing a high-performance computing solution to various industries. The announcement of the SiFive Performance P870 and SiFive…
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SiFive Announces Differentiated Solutions for Generative AI and ML Applications Leading RISC-V into a New Era of High-Performance Innovation
Santa Clara, Calif., Oct. 11, 2023 –SiFive, Inc., the pioneer and leader of RISC-V computing today announced two new products designed to address new requirements for high performance compute. The SiFive…
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Semidynamics and Signature IP Expand Multi-Core RISC-V and CHI Options
Two relatively new players in the CPU world, Semidynamics and Signature IP, have announced multi-core RISC-V and CHI interconnect IP for compute-intensive applications like AI/ML. As some experts predict the…
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Embedded Computing Design Announces Innovative Content Opportunities for RISC-V Summit
Scottsdale, AZ (Oct. 9, 2023) -- Embedded Computing Design (ECD), the leading global media source covering IoT, AI/ML, Security, Power, and Industrial applications, today announced its innovative content opportunities for the…
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Exploring RISC-V Assembly in the Web Browser with SharpRISCV
In the ever-evolving landscape of computer architecture, RISC-V has emerged as an open-source instruction set architecture (ISA), gaining popularity for its simplicity, flexibility, and scalability. One intriguing development in this space…
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Trikarenos is a RISC-V chip for miniaturized space missions
Researchers at the Swiss public university ETH Zurich have developed Trikarenos, a RISC-V-based microcontroller designed to operate reliably in harsh environments like space. Trikarenos can withstand radiation-induced single event upsets…
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Linux Patches Updated For 64-Core RISC-V Milk-V Pioneer mATX Board
The latest Linux kernel patches for enabling the Milk-V Pioneer board have been posted, which is that interesting 64-core RISC-V micro-ATX board with two PCIe x16 slots and more. The…
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Boffins propose RISC-V microcontroller to power cubesats
RISC-V's open source instruction set has attracted a lot of attention over the past few years and not just here on Earth - a team at ETH Zurich in Switzerland…
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RISC-V video editing tested on a Lichee Pi 4A mini PC
If you are interested in learning more about how a mini PC can be used for video editing. You might be interested in a new demonstration of the video editing…
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RISC-V: Pioneering Windows Assembly – A New Era in Computing
The world of computer architecture is constantly evolving, with new innovations reshaping the way we interact with technology. In recent years, one of the most exciting developments has been the…
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SemiDynamics teams for multicore RISC-V chiplet boost
Semidynamics in Spain has teamed up with SignatureIP in the US to combine multi-core RISC-V IP with CHI interconnect for the development of the latest chiplet AI chips. SignatureIP’s Coherent…
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Samsung To Build Next-Gen Tenstorrent AI Chiplet Leveraging RISC-V Architecture
AI chip manufacturing firm, Tenstorrent, has announced a collaboration with Samsung Foundry to develop next-gen cutting-edge chiplets based on its RISC-V architecture. Samsung's Foundry Division Receives a Boost With Tenstorrent Deal For…
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Tenstorrent Selects Samsung Foundry to Manufacture Next-Generation AI Chiplet
SANTA CLARA, CA – Oct. 2, 2023 Tenstorrent, a company that sells AI processors and licenses AI and RISC-V IP, announced today that it selected Samsung Foundry to bring Tenstorrent’s next…
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Semidynamics and SignatureIP create a fully tested RISC-V multi-core environment and CHI interconnect
Barcelona, Spain – 3 October, 2023 -- There is an ever-increasing demand for more powerful chip designs for advanced applications, such as AI and ML, that require many cores on one chip. To…
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[VIDEO] RISC-V Video Editing & 500th Episode
Kdenlive video editing on a Lichee Pi 4A single board computer. Sipeed made it work! This is also the 500th ExplainingComputers video and a celebration thereof. Watch the full video.…
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Automated Kernel Testing on RISC-V Hardware
At Codethink we have an increasing interest in the RISC-V architecture, and have, in past years, written several articles related to it, on subjects ranging from fixing a RISC-V kernel space…
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Ashling’s RiscFree™ SDK Now Supports RISC-V® Processor Cores from CAST
CAST BA51 and BA53 IP core customers can now use Ashling’s RiscFree™ SDK to develop and debug systems that use these RISC-V processors Woodcliff Lake, New Jersey and Limerick, Ireland — September…
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Chipmakers, Researchers, and Hobbyists Show Off the Many Faces of RISC-V
In this roundup, we review the ways RISC-V is making its mark in the computing world—from small-scale gaming projects to large-scale corporate initiatives. While the royalty-free RISC-V instruction set architecture…
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OpenHW Group Appoints Florian ‘Flo’ Wohlrab as New CEO to Spearhead Open-Source Ecosystem Advancement
OTTAWA, Canada – September 20, 2023 - OpenHW Group, a global consortium driven by its members and contributors, is pleased to announce the appointment of Florian ‘Flo’ Wohlrab as its new…
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Accelerating RISC-V development with network-on-chip IP
In the world of system-on-chip (SoC) devices, architects encounter many options when configuring the processor subsystem. Choices range from single processor cores to clusters to multiple core clusters that are…
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Claude (AI) Codes a RISC-V Core in TL-Verilog
TL-Verilog has the promise to help humans and LLMs collaborate effectively and safely on digital circuits. But first, we need to teach LLMs TL-Verilog. I explore the ability of today's…
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Nordic Semiconductor proves world-leading processing efficiency with the revolutionary nRF54H20 SoC
Nordic Semiconductor today announces that its nRF54H20 multiprotocol System-on-Chip (SoC)—the first in the nRF54H Series—has proven its world-leading processing efficiency, along with superior processing performance. This underscores the revolutionary potential…
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New RISC-V Market Report Will Provide 5-Year Growth Projections for Semiconductor Devices and Insights on the Enabling Ecosystem
SAN JOSE, CA / ACCESSWIRE / September 19, 2023 / The SHD Group, a leading strategic marketing and business development firm, today announced its plans to create a detailed market research…
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New RISC-V Market Report Will Provide 5-Year Growth Projections for Semiconductor Devices and Insights on the Enabling Ecosystem
SAN JOSE, CA / ACCESSWIRE / September 19, 2023 / The SHD Group, a leading strategic marketing and business development firm, today announced its plans to create a detailed market research…
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[VIDEO] Pointers in RISC-V Assembly
In this video, we translate a C program to RISC-V assembly to demonstrate how pointers are declared and referenced. We also use base instructions to set memory locations. Watch the…
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Esperanto Technologies Introduces First Generative AI Appliance Based on RISC-V, Enabling Developers to Easily Create and Deploy Purpose-Built Vertical Applications
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Esperanto Technologies™, the leading developer of high-performance, energy-efficient artificial intelligence (AI) and high-performance computing (HPC) solutions based on the RISC-V instruction set, today announced the industry’s first…
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Esperanto Technologies Introduces First Generative AI Appliance Based on RISC-V, Enabling Developers to Easily Create and Deploy Purpose-Built Vertical Applications
MOUNTAIN VIEW, Calif., September 12, 2023 – Esperanto Technologies™, the leading developer of high-performance, energy-efficient artificial intelligence (AI) and high-performance computing (HPC) solutions based on the RISC-V instruction set, today announced…
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Bluespec’s accelerate-HLS leverages RISC-V to simplify and speed the development of HLS applications
Bluespec has announced its new Accelerate-HLS tool supports Siemens’ Catapult™ software for high-level synthesis and Bluespec RISC-V cores with coherent physical memory. Bluespec, Inc. unveiled its new Accelerate-HLS tool that…
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Bluespec’s Accelerate-HLS Leverages RISC-V to Simplify and Speed the Development of HLS Applications
FRAMINGHAM, Mass.--(BUSINESS WIRE)--Bluespec, Inc. unveiled its new Accelerate-HLS tool that simplifies and speeds the development of hardware using High-Level Synthesis (HLS) by offloading complex functionality that RISC-V processors can more effectively implement. Memory…
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Configurable LLDB for (not only) embedded RISC-V processors
At some point, software developers or processor developers need to check and debug their code. They can do this at different levels, for example looking at waves or parsing printouts,…
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Andes Announces General Availability of the New AndesCore™ RISC-V Multicore Vector Processor AX45MPV
Hsinchu, Taiwan – Sep. 7, 2023 – Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today proudly announces general availability of the…
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What is RISC-V, and why we’re unlocking its potential
As you may have read, we recently announced our commitment to accelerate the availability of the RISC-V open-standard ecosystem and platform by signing on as founding members of a new…
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Codasip collaborates with Siemens to deliver trace solution for custom processors
Codasip has announced its collaboration with Siemens to offer the Tessent Enhanced Trace Encoder solution with its customizable RISC-V codes. Codasip®, the leader in RISC-V Custom Compute, now offers the…
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Andes Announces General Availability of the New AndesCore™ RISC-V Multicore Vector Processor AX45MPV
Hsinchu, Taiwan – Sep. 7, 2023 – Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today proudly announces general availability of the…
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RISC-V Summit China: Experts praise open source architecture for driving tech innovation and change
RISC-V is an open source instruction set architecture, which allows people to build and customize computer processors for a wide range of needs. It's been praised for driving technological innovation…
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Codasip collaborates with Siemens to deliver trace solution for custom processors
Munich, Germany, 5 September 2023 – Codasip®, the leader in RISC-V Custom Compute, now offers the Tessent™ Enhanced Trace Encoder solution from the Tessent Embedded Analytics product line at Siemens…
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GOWIN Semiconductor & Andes Technology Corp. Announce The First Ever RISC-V CPU and Subsystem Embedded 22nm SoC FPGA
San Jose, August 29, 2023 - Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of…
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SiFive unveils P870 high-performance core, discusses future of RISC-V
SiFive has just given a presentation at Hot Chips 2023 introducing the new high-performance P870 RISC-V core and its automotive equivalent the P870-A core, plus discussing RISC-V in general, its…
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Sipeed unveils RISC-V tablet, portable Linux console, and cluster
Sipeed has unveiled three new hardware platforms based on the LM4A RISC-V system-on-module found in their LicheePi 4A SBC, namely the Lichee Cluster 4A cluster for native RISC-V compilation, the Lichee Pad 4A 10.1-inch tablet running Android…
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Nuclei , the World’s First RISC-V CPU IP Vendor to Accomplish ISO 26262 ASIL-D Product Certificate
Nuclei System Technology, a leading RISC-V CPU IP vendor in China, announced that NA900 has been certified to be compliant to ASIL D requirements of ISO 26262 standards for both systematic…
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Think and Tinker your own IoT solutions
This versatile single-board computer (SBC) is powered by a 64-bit RISC-V-based processor, which supports both Linux Debian and Yocto operating systems. Tinker V packs features rich connectivity into a compact…
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LIVE WEBINAR: Accelerating Compute-Bound Algorithms with Andes Custom Extensions (ACE) and Flex Logix Embedded FPGA Array
RISC-V have great adoption and momentum. One of the key benefits of RISC-V is the ability for SoC designers to extend its instruction sets to accelerate specific algorithms. Andes’ ACE (Andes…
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RISC-V – Part 2 : Ambitious Aims
In RISC-V Part 1 : Origins and Architecture we looked at the origins of the RISC-V ISA and had the briefest of overviews of the instruction set. In this post, we’re going…
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RISC-V Summit China 2023 kicks off in Beijing
Enthusiasts of the open-source instruction set RISC-V have gathered at this venue in the Chinese capital. Just a few years ago, the community in China was considered small. But these…
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RISC-V Customization Gets A Standing Ovation
Processor vendors have always tried to create a large software ecosystem around their products, because it creates stickiness and it naturally “locks-in” large numbers of customers who have invested in…
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Milk-V Launches Milk-V Vega, the World’s First RISC-V Open Source 10 Gigabit Ethernet Switch
August 22, 2023 -- Shenzhen MilkV Technology Co., Ltd (Milk-V) unveiled the world’s first RISC-V open-source 10-gigabit Ethernet switch - the Milk-V Vega. The core control chip utilizes the FSL1030M network…
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OpenHW announces tape out of RISC-V-based CORE-V MCU Devkit
Available for order the OpenHW CORE-V MCU DevKit includes an open-source printed circuit board (PCB) which integrates OpenHW’s CORE-V MCU and various peripherals, a software development kit (SDK) with a…
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Valtrix to Exhibit at RISC-V Summit China August 23-25
BANGALORE, India, Aug. 22, 2023 /PRNewswire/ -- Valtrix, a provider of design verification products for creating accurate CPU and system-on-chip implementations, is set to participate in the upcoming RISC-V Summit at the Shangri-La…
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RISC-V Specialist Milk-V Jumps Into the Network Market with the New 10-gig-E Vega Switch
RISC-V specialist Milk-V has announced yet another new product built atop the free and open source instruction set architecture, but unlike its previous single-board computer (SBC) designs this one's a…
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Lichee Pi 4A RISC-V Desktop Gets Unboxed, Offers Strong Linux Performance
As RISC-V continues to develop, so does the plethora of products around the open source processor. Unlike the Raspberry Pi which uses proprietary ARM processors, the new Lichee Pi 4A uses open source RISC-V…
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New Emulator Lets Some x86-64 Games Run on RISC-V Dev Board
The latest version of Box64, a popular x86_64 emulator for Linux running on architectures like ARM/AArch64 and RISC-V, introduces significant performance improvements, making possible gaming on RISC-V-based platforms such as the Vision Five 2 board, reports Phoronix. Read the full article.
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OpenHW Group Delivering RISC-V CORE-V MCU Dev. Kits
Ottowa, Ontario. OpenHW Group is now shipping its OpenHW CORE-V MCU DevKit featuring an open-source printed circuit board (PCB) with OpenHW’s CORE-V MCU, several peripherals, a software development kit (SDK) with Eclipse-based integrated…
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World’s First RISC-V Laptop Roma Officially Delivered: 8GB RAM and Pre-installed with Domestic OS
The world’s first laptop designed for RISC-V development, the Roma laptop, has been officially delivered to customers. The laptop is powered by a high-quality RISC-V processor with a quad-core 1.5GHz…
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OpenHW Group Announces Tape Out of RISC-V-based CORE-V MCU Development Kit for IoT Built with Open-Source Hardware & Software
OTTAWA, Canada – August 16, 2023 - OpenHW Group today announced that the industry’s most comprehensive Development Kit for an open-source RISC-V MCU is now available to be ordered. The OpenHW CORE-V…
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OpenHW Group Announces Tape Out of RISC-V-based CORE-V MCU Development Kit for IoT Built with Open-Source Hardware & Software
OTTAWA, Canada – August 16, 2023 - OpenHW Group today announced that the industry’s most comprehensive Development Kit for an open-source RISC-V MCU is now available to be ordered. The OpenHW CORE-V…
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Collaboration looks to build AI Accelerator chip with analogue in-memory computing
Andes Technology, a supplier of 32/64-bit RISC-V processor cores and TetraMem, a developer of analogue memristor technology and in-memory computing, are collaborating on the development of a fast, highly efficient,…
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Leading semi players join forces to accelerate RISC-V
Semiconductor industry players Robert Bosch GmbH, Infineon Technologies AG, Nordic Semiconductor, NXP Semiconductors, and Qualcomm Technologies Inc., have come together to jointly invest in a company aimed at advancing the…
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Andes Technology And TetraMem Collaborate To Build Groundbreaking AI Accelerator Chip With Analog In-Memory Computing
San Jose, CA - Aug 10, 2023 - Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, and TetraMem Inc, a…
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AI and RISC-V chip company Tenstorrent raises $100m from Hyundai, Kia, and Samsung
AI chip company Tenstorrent has raised $100 million from investors including Hyundai Motor Group, Kia, and a Samsung investment fund. The investment in the AI and RISC-V startup was structured…
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Big chip players join forces to form another RISC-V venture
The RISC-V open instruction set architecture got a boost today after it emerged that five chip giants are coming together to jointly invest in a company to develop reference architectures…
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Forlinx announces RISC-V SoM based on StarFive JH7110
Forlinx announced in July that they are working together with the RISC-V processor manufacturer StarFive to deliver the FET7110-C System-on-Chip based specifically on the Jinghong 7110 with RISC-V architecture. The…
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Terapines ZCC Toolchain Fully Supports Andes RISC-V Processors
Wuhan, China, July 31, 2023 (GLOBE NEWSWIRE) -- Terapines Technology, an innovative provider of software/hardware co-design solutions announces the full support for Andes RISC-V processors lineup in the Terapines ZCC…
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Chip makers team up to take on Arm with RISC-V
Five companies that manufacture semiconductors for smartphones, automobiles and more have announced that they will form a company designed to advance the open source RISC-V architecture, in a move widely…
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AI chip startup Tenstorrent lands $100M investment from Hyundai and Samsung
The appetite for hardware to train AI models is voracious. AI chips are forecast to account for up to 20% of the $450 billion total semiconductor market by 2025, according…
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Confidence In AI Startup Tenstorrent Spurs $100M Funding Round By Hyundai And Samsung
Scrappy AI chip and technologies startup Tenstorrent announced today that it has secured another major $100M round of funding from new marquee partners Hyundai Motor Group and Samsung Catalyst Fund.…
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RISC-V AI Startup Tenstorrent Gets Another $100M Infusion From Samsung And Hyundai
Jim Keller is a man who should need no introduction to an audience of tech nerds. He was part of the team that developed the legendary DEC Alpha microprocessors back…
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IIT Madras invites Applications for Symposium on ‘Future of India’s Electronics and Computers’
Read the full article.
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Krakatoa Technologies Celebrates Key Milestone as RISC-V Core Startup with Big Order from PT Andreal Industri Primatama
SINGAPORE, August 2, 2023/EINPresswire.com/ -- Krakatoa Technologies, an agile RISC-V core startup, is thrilled to announce a momentous milestone in its growth trajectory. Today, PT Andreal Industri Primatama, a prominent player in the…
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Terapines ZCC Toolchain Fully Supports Andes RISC-V Processors
Wuhan, China, July 31, 2023 - Terapines Technology, an innovative provider of software/hardware co-design solutions announces the full support for Andes RISC-V processors lineup in the Terapines ZCC toolchain. The ZCC toolchain delivers proven…
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Terapines ZCC Toolchain Fully Supports Andes RISC-V Processors
Wuhan, China, July 31, 2023 - Terapines Technology, an innovative provider of software/hardware co-design solutions announces the full support for Andes RISC-V processors lineup in the Terapines ZCC toolchain. The ZCC toolchain delivers proven…
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Esperanto Merging HPC and ML in Upcoming RISC-V Processor
Esperanto Technologies has ambitious plans for its next RISC-V processor: to undo the accelerator model and build a chip that has both CPU and GPU capabilities for machine learning and…
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RISC-V Finds Its Foothold in a Rapidly Evolving Processor Ecosystem
Since its emergence close to a decade ago, RISC-V quickly gained the support of major chip makers, including Apple, which has put controllers in its Apple Silicon. About 10 billion chip cores…
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AMD Readies “New Stuff” For Linux 6.6 Graphics Driver, AMDGPU DC For RISC-V
Sent out today was a batch of "new stuff" for the AMDGPU and AMDKFD kernel graphics drivers for queuing in DRM-Next ahead of the Linux 6.6 merge window opening in…
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Semidynamics Released its 4-way Atrevido 423 RISC-V Core
Barcelona, Spain. Semidynamics released its 64-bit flexible 4-way Atrevido 423 RISC-V core delivering double the instructions than the 2-way, 223 core. More functioning units are utilized increasing the IPC (instructions-per-cycle). The processor…
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Semidynamics Released its 4-way Atrevido 423 RISC-V Core
Barcelona, Spain. Semidynamics released its 64-bit flexible 4-way Atrevido 423 RISC-V core delivering double the instructions than the 2-way, 223 core. More functioning units are utilized increasing the IPC (instructions-per-cycle). The processor…
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AMD Readies “New Stuff” For Linux 6.6 Graphics Driver, AMDGPU DC For RISC-V
Sent out today was a batch of "new stuff" for the AMDGPU and AMDKFD kernel graphics drivers for queuing in DRM-Next ahead of the Linux 6.6 merge window opening in…
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RISC-V Finds Its Foothold in a Rapidly Evolving Processor Ecosystem
Developers have grown up hearing ARM or x86 being the guts of PCs and servers, but an alternative architecture called RISC-V is emerging. In the next few years, some companies will inevitably…
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Re-Targetable LLVM C/C++ Compiler For RISC-V
RISC-V is a modular instruction set architecture (ISA) with great customization capabilities that enable innovation and differentiation without fragmentation. On top of the baseline modules from ratified/standard ISA extensions, such…
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Re-Targetable LLVM C/C++ Compiler For RISC-V
RISC-V is a modular instruction set architecture (ISA) with great customization capabilities that enable innovation and differentiation without fragmentation. On top of the baseline modules from ratified/standard ISA extensions, such…
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Semidynamics announces fully customisable, 4-way Atrevido 423 RISC-V core for big data applications
Barcelona, Spain – 20 July, 2023. Semidynamics, the only provider of fully customisable RISC-V processor IP, has launched the next member of its Atrevido family of 64-bit cores. The Atrevido…
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Vitra-XS Debug & Trace Probe
Vitra-XS is Ashling’s Debug & Trace Probe for embedded development with support for multiple target architectures including RISC-V, Arm and Synopsys ARC powered systems. Vitra-XS works with Ashling’s RiscFree™ SDK for advanced embedded system…
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Debian GNU/Linux Is Now Officially Supported on the RISC-V Architecture
The Debian Project announced today that the RISC-V (riscv64) hardware architecture is now officially supported by the Debian GNU/Linux operating system. Until today, Debian was officially supported on 64-bit (amd64), 32-bit (i386),…
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Leveraging RISC-V architecture to boost economic development
The revolution in computing is unfolding in an unlikely place – not just in the world’s Silicon Valley but potentially in third-world countries. The harbinger of this change is RISC-V,…
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Ashling announce RiscFree™ support for MachineWare’s SIM-V RISC-V Instruction Set Simulator.
Limerick, Ireland. 29th May 2023 - Ashling announced today that Ashling’s RiscFree SDK now provides target debug support for MachineWare’s SIM-V RISC-V Instruction Set Simulator. RiscFree is Ashling’s SDK including…
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Semidynamics announces fully customisable, 4-way, Atrevido 423 RISC-V core
The Atrevido 423 has a wider, 4-way pipeline, allowing for the decoding and retirement of up to two times more instructions than its recently launched, 2-way, 223 core. It is…
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RiscFree C/C++ support for Lattice RISC_V soft IP cores
Ashling has added support for RISC-V soft IP cores from Lattice Semiconductor to its RiscFree development tool. The RiscFree software development kit (SDK) includes an IDE, compiler and debugger, which…
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Semidynamics announces, 4-way, Atrevido 423 RISC-V core
Semidynamics has launched the next member of its Atrevido family of 64-bit cores. The Atrevido 423 h... Read more at: https://www.bisinfotech.com/semidynamics-announces-4-way-atrevido-423-risc-v-core/
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RISC-V Fast-Forwards, Breaks Ground for Auto Innovations
The SiFive RISC-V Automotive CPU IP continues to advance to address and enable automotive applications like infotainment, connectivity and advanced driver-assistance systems. Yet without the right tools, embedded software developers…
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Want Tailormade Screamingly-High-Performance RISC-V64 IP?
Soooo… you’ve decided you’re going to create a system-on-chip (SoC) device of such awesomeness that it will leave your competitors gnashing their teeth and rending their garb. You’ve also decided…
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Fully customisable 4-way RISC-V core for big data
Semidynamics in Spain has developed a customisable 4-way RISC-V 64bit core for data centre chips. The Atrevido 423 RISC-V core has a wide 4-way pipeline for decoding and retiring twice…
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ANDLA DEBUTS FOR AI ACCELERATION
Andes’ new deep-learning accelerator addresses convolutional neural networks in edge applications. Accompanied by vector CPUs, it forms an AI subsystem that can be scaled up for higher vision- and audio-workload…
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Making the most of the 60th DAC
I just returned from a week in San Francisco where I attended the 60th Design Automation Conference. It was a typical week at DAC — cold weather in July, catching up with long-time industry…
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Polos CH32Vxx 32-bit RISC-V MCU boards starts at $1.99
XPU Labs, a subsidiary of AnalogLamb, has designed three inexpensive “Polos” development boards based on WCH CH32VXX RISC-V microcontrollers with pricing starting at just $1.99. The three development/breakout boards have the…
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Startups Help RISC-V Reshape Computer Architecture
The RISC-V instruction set architecture (ISA) is one of the most notable contenders to emerge in the ever-evolving realm of computer architecture. Because of its modularity, RISC-V provides more flexibility…
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RISC-V Fast-Forwards, Breaks Ground for Auto Innovations
The SiFive RISC-V Automotive CPU IP continues to advance to address and enable automotive applications like infotainment, connectivity and advanced driver-assistance systems. Yet without the right tools, embedded software developers…
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The industry’s first RISC-V IoT security chip, “Towngas Chip”, had sold over 1,000,000 pieces
July 17, 2023 -- Towngas Group officially announced that the sales of the first RISC-V IoT security chip "Towngas Chip" had exceeded 1 million pieces, which marks that the RISC-V open-source…
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THIS RISC-V CPU GAMES IN RUST FROM INSIDE THE GAME
has created something truly impressive — a working RISC-V CPU completely contained in a Terraria world. And then for added fun, he wrote the game of pong, playable in real time,…
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DAC 2023: RISC-V is not in the future, it’s now
At this year’s Design Automation Conference (DAC), there was a panel discussion entitled, “Delivering on RISC V’s Promise to Give Designers Freedom to Innovate – What’s Needed?”. A key message…
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PODCAST: RISC-V International, Today and Tomorrow with Calista Redmond
Dan is joined by Calista Redmond, CEO of RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic…
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VIDEO: DAC 2023, Day 3: ‘CHIPS Acts,’ RISC-V, More AI
In this video report, EE Times reporters Sally Ward-Foxton and Nitin Dahad discuss what they saw and heard at the third day of the Design Automation Conference (DAC) 2023, in San…
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AnalogLamb Announces RISC-V Polos Development Boards, Starting at Just $1.99
Beijing-based embedded hardware specialist AnalogLamb has announced three new low-cost entries in its Polos family of development boards, all powered by RISC-V microcontrollers from WCH Electronics — and with prices…
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BeagleV®-Ahead single board computer available from Farnell
Farnell is now stocking the newly introduced BeagleV®-Ahead, the first professional, open-source mass production RISC-V single board computer (SBC) by Beagleboard.org®. BeagleV®-Ahead is in the same form factor and has…
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BeagleBoard.org Moves Along with its BeagleV-Ahead
BeagleBoard.org is now delivery its BeagleV-Ahead single board computer (SBC) based on the TH1520, a quad core 64-bit RISC-V SoC from T-Head. The SBC utilizes the open-source RISC-V instruction set architecture (ISA).…
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BeagleV-Ahead is a single-board RISC-V computer that’s compatible with BeagleBone add-ons
BeagleBoard has launched a new single-board computer called the BeagleV-Ahead. It’s the same shape as the company’s BeagleBone Black and it’s compatible with some accessories designed for that board. But instead of an…
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BeagleV-Ahead RISC-V computer from BeagleBoard.org available now under $150
BeagleBoard.org®, a leading developer of open-source hardware platforms, is thrilled to announce the highly anticipated launch of BeagleV® Ahead, an innovative single board computer (SBC) based on TH1520, a quad core…
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Bluespec’s newest RISC-V chip adds customization capabilities for edge workloads
Bluespec, a RISC-V tools and silicon IP provider, has introduced a processor design based on the open standard RISC-V instruction set architecture that will allow more customization based on the…
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VIDEO: A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs
A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs Lukas Gerlach (CISPA Helmholtz Center for Information Security), Daniel Weber (CISPA Helmholtz Center for Information Security), Ruiyi Zhang (CISPA Helmholtz Center…
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Towards a RISC-V Open Platform for Next-generation Automotive ECUs
Abstract—The complexity of automotive systems is increasing quickly due to the integration of novel functionalities such as assisted or autonomous driving. However, increasing complexity poses considerable challenges to the automotive…
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Imperas details verification of automotive AI RISC-V vector processor IP
Imperas Software in the UK and Cadence Design Systems have detailed the verificaiton flow for NSITEXE developing an automotive AI RISC-V processor core. The two worked on a comprehensive verification…
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LicheePi 4A RISC-V SBC gets 16GB/128GB version, metal enclosure, 10.1-inch display, and more accessories
LicheePi 4A quad-core RISC-V SBC is now available with 16GB RAM and 128GB eMMC flash, and Sipeed has also introduced various accessories such as a metal enclosure, a 10.1-inch touchscreen…
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Upcoming low cost RISC-V breakout boards start at $1.99
AnalogLamb is set to release three affordable RISC-V breakout boards. These boards are based on the CHV32 Series microcontrollers offering support for standard interfaces such as I2C, SPI, UART, CAN,…
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Cadence and Imperas Support NSITEXE in the Development of Advanced RISC V Vector Processor IP for Automotive AI Applications
Oxford, United Kingdom, July 10th, 2023 — Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Cadence Design Systems, Inc. (Nasdaq: CDNS) has collaborated with Imperas to enable NSITEXE,…
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Takeaways From the First RISC-V Summit Europe
RISC-V, a free and open source instruction-set architecture (ISA), has gained significant traction from both industry giants and emerging startups. A simple, scalable design, coupled with the ability to customize…
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VIDEO: Running LVGL Application on RT-Smart MicroKernel OS with RISC-V
Recap of the 2023 RT-Thread Global Tech Conference: Today, we’re excited to feature HIMA, a passionate engineer with experience in developing embedded systems. Currently pursuing her Master’s degree in Germany,…
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The growth of RISC-V across industries
RISC-V has seen significant momentum during the past year. According to RISC-V International there are over 10 billion RISC-V cores on the market, with thousands of engineers working on RISC-V…
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Imperas Helps Navigate the Journey to RISC-V Based Silicon at DAC 2023
Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced its participation at DAC 60 with panels and presentations, and exhibits and live demos at its booth 2336.…
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Takeaways From the First RISC-V Summit Europe
RISC-V, a free and open-source instruction set architecture (ISA), has gained significant traction from both industry giants and emerging startups. A simple, scalable design, coupled with the ability to customize…
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The Next Revolution in the Microchip Industry
As microchips increasingly become an integral part of our lives, share prices for many companies that make them are rising fast. Last week shares of NVIDIA Corp (NVDA) jumped over 30%,…
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HPCpodcast: An Architecture Update from RISC-V International CTO Mark Himelstein
Mark Himelstein, chief technology officer at RISC-V International, joins us to discuss the latest developments with the RISC-V instruction set architecture and its growing community and footprint. Topics include: HPC use…
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Power, automotive and AI markets highly interested in RISC-V
At the recent SiFive RISC-V China Technology Forum that took place in Shenzhen, China, SiFive chief architect and the chairman of RISC-V International Krste Asanović noted that the momentum of…
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It’s all about RISC-V code size
Here at Codasip we’re passionate about reducing the code size of our RISC-V cores for our customers, but why? Are we not making the core larger and more complex as…
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Bluespec’s MCUX RISC-V Processor Ideal for FPGAs and ASICs
Framingham, Massachusetts. Bluespec Inc. released its MCUX RISC-V processor designed to simplify the integration of customize protocols and add accelerators to FPGAs and ASICs. The platform is ideal for solutions that…
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VIDEO: EUPILOT: Europe’s HPC and AI pre-exascale accelerator demonstrator
The EUPILOT project aims to establish a European-based accelerator platform for high-performance computing (HPC) and AI. It seeks to achieve European digital sovereignty in HPC, promote the adoption of the RISC-V ecosystem, and cater to diverse…
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Tiempo Secure’s new TESIC RISC-V IP successfully passes SERMA CC EAL5+ security assessment tests
Grenoble, France – July 3, 2023 – Tiempo Secure’s latest TESIC design, a Secure Element targeting applications such as iSIM, eSE, Payment, UWB, Digital ID, IoT security and Mobile Application Processors,…
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VMware join hands with Samsung, AMD, RISC-V for confidential computing
VMware recently announced at the Confidential Computing Summit 2023 that it is partnering with chipmakers Samsung, AMD, and the RISC-V Keystone community for a project to help accelerate the adoption of confidential computing.…
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Tiempo Secure’s new TESIC RISC-V IP successfully passes SERMA CC EAL5+ security assessment tests
Grenoble, France – July 3, 2023 – Tiempo Secure’s latest TESIC design, a Secure Element targeting applications such as iSIM, eSE, Payment, UWB, Digital ID, IoT security and Mobile Application Processors,…
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VMware, Other Tech Giants Announce Push for Confidential Computing Standards
In conjunction with the 2023 Confidential Computing Summit last week, VMware announced a partnership with tech giants to accelerate the development of confidential computing applications. Confidential computing relies on a…
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Customizable RISC-V processor is vendor-independent
Bluespec’s MCUX RISC-V processor allows developers to implement custom instructions and add accelerators to FPGAs and ASICs. MCUX joins the company’s MCU RISC-V family of processors designed for ultra-low resource…
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Chinese Researchers Used AI to Design RISC-V CPU in Under 5 Hours
A group of Chinese scientists has published (PDF) a paper titled "Pushing the Limits of Machine Design: Automated CPU Design with AI." The paper details the researchers' work in designing a new…
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VMware, AMD, Samsung and RISC-V push for confidential computing standards
VMware has joined AMD, Samsung, and members of the RISC-V community to work on an open and cross-platform framework for the development and operation of applications using confidential computing hardware.…
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VMware partners with Samsung, AMD and RISC-V to accelerate confidential computing
VMware Inc. stepped up its efforts to accelerate the adoption of confidential computing today, announcing an alliance with chipmakers Samsung Electronics Co. Ltd. and Advanced Micro Devices Inc., as well as the RISC-V Keystone community.…
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China Mobile releases two self-developed RISC-V communications chips
China Mobile recently released the world's first LTE-Cat.1 chip with pure self-developed RISC-V architecture, as well as its first pure self-developed mass-production cellular IoT communications chip, according to Ijiwei, a Chinese…
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The European Project Creating Extensible, Energy-Efficient RISC-V CPUs
Some European researchers are developing open-source RISC-V cores to compete with x86 and Arm, and are relying on only €8 million in funding. Details about the ambitious eProcessor project were…
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Tailor Made RISC-V Performance – eeNews interview with Roger Espasa/Semidynamics
The RISC-V Instruction Set Architecture is perfectly suitable for fine tuning the performance depending on the application. In this interview Roger Espasa, CEO and Founder at Semidynamics Technology Services explains…
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In Her Own Words: Calista Redmond, casual Fridays and collaboration
Sometimes we learn from our own mistakes, but the errors of others also influence us. Which is why Calista Redmond’s leadership style differs dramatically from one of the first CEOs…
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RISC-V Europe Summit Debuts Among Signs of Significant Growth in Advanced IoT Applications
The first RISC-V Summit Europe, held in Barcelona, Spain, from June 5-9, highlighted RISC-V International’s commitment to expanding the software ecosystem for the architecture and removing any remaining obstacles to…
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RISC-V: The Game-Changer In Microprocessor Investments. Here’s 3 Companies Riding The Wave.
The tech sector has always been an area where new technology emerges every few years. However, when it comes to microprocessors, the industry has mostly been dominated by only a…
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Could RISC-V Disrupt the 8086-Arm Hegemony?
The recent RISC-V Summit Europe brought together developers, architects, executives, and policymakers across the global RISC-V ecosystem. Attendees from academia, government, research, SMEs, industry, and open-source communities gathered to share knowledge, ideas,…
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XMOS Joins RISC-V Ecosystem
Fabless semiconductor company XMOS has designed the 4th generation of its Xcore architecture to be RISC-V compatible. The company’s microarchitecture enables creation of a system-on-chip (SoC) using software programmability, allocating…
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Semidynamics announces largest, fully customisable Vector Unit in the RISC-V market, delivering up to 2048b of computation per cycle for unprecedented data handling
Barcelona, Spain – 1 June, 2023. Semidynamics has announced its new, entirely customisable Vector Unit to go with its innovative range of fully customisable 64-bit RISC-V cores. The Vector Unit is totally compliant…
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XMOS Joins RISC-V Ecosystem
Fabless semiconductor company XMOS has designed the 4th generation of its Xcore architecture to be RISC-V compatible. The company’s microarchitecture enables creation of a system-on-chip (SoC) using software programmability, allocating…
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The Next Revolution in the Microchip Industry
As microchips increasingly become an integral part of our lives, share prices for many companies that make them are rising fast. Last week shares of NVIDIA Corp (NVDA) jumped over 30%,…
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Secure-IC & NSITEXE extend strategic partnership to provide security solutions for Cyber-Physical Systems (CPS)
Cesson-Sévigné (France) and Tokyo (Japan) – June 15th, 2023 – Secure-IC, the rising leader, and the unique global provider of end-to-end cybersecurity solutions for embedded systems and connected objects, announces today…
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What is RISC-V?
Even for computing hobbyists, RISC-V is a bit in the weeds, but perhaps not for long. It's one of the rising stars in the computing world and is one of…
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RISC-V rises to software ecosystem challenge
RISC-V, the open standard instruction set architecture (ISA) alternative to Intel and ARM, held its first European summit on 5 to 9 June 2023 in Barcelona. Originally developed in 2010…
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DFRobot Launches the All-In-One UNIHIKER, a Single-Board Arm Computer with Display and RISC-V MCU
DFRobot has announced the launch of a new all-in-one single board computer (SBC) development platform, designed for plug-and-play programming and bringing its own 2.8" touchscreen along for the ride: the…
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Milk-V Unveils Its Third RISC-V Board in a Month: The $9 Dual-Core Linux-Capable Milk-V Duo
RISC-V startup Milk-V has announced yet another development board built around the free and open source instruction set, this time a compact development device clearly inspired by the Raspberry Pi…
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RISC-V gathers pace in Europe
The RISC-V Summit Europe brought together developers, architects, technical decision and policy makers from across European RISC-V ecosystem for the first time in the region this week. Attendees from academia,…
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Startup plans customizable RISC-V edge AI speech processor | Nick Flaherty, EE News Europe
AONDevices has developed an efficient edge AI denoising technology for applications that require minimal power and latency running on its forthcoming accelerator IP and hardware as well as third party…
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Imagination, GHS team for RTOS and tools on RISC-V CPUs | Nick Flaherty, EENews Europe
Green Hills Software has ported its µ-velOSity safety- and security-certified real-time operating system (RTOS) to the real time RISC-V cores developed by Imagination Technologies, with plans to support Imagination’s Catapult…
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Agile Analog launches first complete RISC-V analog IP subsystem at RISC-V Summit Europe
Agile Analog, the customisable analog IP company, is launching the first complete analog IP subsystem for RISC-V applications at the RISC-V Summit Europe in Barcelona (5-9 June). The initial subsystem…
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Interview with Calista Redmond – RISC-V summit Barcelona
At the RISC-V summit in Barcelona eeNews is meeting up with Calista Redmond. She is the CEO of RISC-V International. In our conversation we are talking about what Europe has…
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Configurable 64-bit RISC-V IP Targets Machine Learning, Other Advanced Apps | Alix Paultre, Electronic Design
Configurable high-bandwidth RISC-V cores with vector units can be made to directly address challenging applications like machine learning, AI, and other cutting-edge spaces. Semidynamics is a European supplier of RISC-V IP…
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Computing at the Ultimate Edge – Space | Wisse Hettinga, EENews Europe
eeNews Europe is meeting up with Gerard Rauwerda, Business Developer with Technolution. We discuss the RISC-V developments over the years and the role Technolution played, but also what specific requirements…
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The RISC-V Report – interviewing the key players (2017-2023)
Take time for the The RISC-V Summit in Barcelona and connect the dots of this Open Instruction Set Architecture In 2017 we had the opportunity to interview Krste Asanovic about…
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Agile Analog launches first complete RISC-V analog IP subsystem
Agile Analog has brought together its customisable IP blocks to create the first complete analog IP subsystem for battery-powered RISC-V chips. The initial subsystem includes all the analog IP required…
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Complete RISC-V analog IP subsystem targets IoT | Jean-Pierre Joosting, EE News Europe
Agile Analog is offering the first complete analog IP subsystem for RISC-V applications at the RISC-V Summit Europe in Barcelona. The initial subsystem includes all the analog IP required for a typical…
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Newly Revealed RISC-V Vector Unit Could Be Used for AI, HPC, GPU Applications | Anton Shilov, Tom’s Hardware
Semidynamics announces high-performance RISC-V IP. Semidynamics has introduced one of the industry's first RISC-V vector units that could be used for highly parallel processors, such as those used for artificial intelligence (AI),…
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Ventana to Deliver Keynote at RISC-V Summit Europe | Yahoo! Finance
Ventana Micro Systems Inc., provider of the highest performance RISC-V processors, today announced its Founder and CEO Balaji Baktha is providing the RISC-V Summit Europe keynote speech at 10:00am on June 6. Ventana will be…
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Adding RISC-V Vector Cryptography Extension support to QEMU
RISC-V is an open source instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. Codethink has been working with the RISC-V CPU architecture for several years. We've…
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Consortium’s Move Will Boost RISC-V Ecosystem, Thankfully | Steve Leibson , EE Times
RISC-V represents an existential threat to Arm, and a new industry consortium plans to increase that threat of extinction by accelerating the development of open-source software for the RISC-V architecture.…
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Alibaba’s T-Head joins global initiative to develop RISC-V software ecosystem, along with Intel, Qualcomm and Nvidia | Ann Cao, South China Morning Post
T-Head, the chip unit of Alibaba Group Holding, has joined a global initiative to develop a software ecosystem and accelerate commercialisation for RISC-V, as the open-source chip design architecture is…
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Milk-V Duo is a $9.00 RISC-V tiny embedded computer | Giorgio Mendoza , Linux Gizmos
The Milk-V Duo is a small RISC-V embedded platform capable of running Linux and RTOS. The low-cost device features up to 26x GPIOs, optional 10/100Mbps Ethernet support and integrated with a…
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RISE project gives RISC-V an open source software lift | Nitin Dahad, Embedded.com
RISC-V Software Ecosystem (RISE) project brings together key players in the ecosystem with a governing board that includes Andes, Google, Intel, Imagination Technologies, MediaTek, Nvidia, Qualcomm Technologies, Red Hat, Rivos,…
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RISE to boost development of open source RISC-V software
Chip designers are at the heart of a new project to boost the development of open source software for the RISC-V instruction set. The RISC-V Software Ecosystem (RISE) Project is…
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UltraRISC Selects Valtrix STING for Verification of RISC-V SoC Designs
BANGALORE, India, June 1, 2023 /PRNewswire/ -- Valtrix Systems, an industry leading provider of RISC-V design verification products for building functionally correct CPU and system-on-chip implementations, announced today that UltraRISC, a leading provider…
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Compiler test update boosts Andes RISC-V in automotive
Andes Technology has upgraded its version of the SuperTest Compiler Test and Validation Suite developed and supplied by Solid Sands in the Netherlands to support its growth in automotive chip…
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Adding RISC-V Vector Cryptography Extension support to QEMU
RISC-V is an open source instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. Codethink has been working with the RISC-V CPU architecture for several years. We've…
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Linux Foundation and pals – including Intel – back software ecosystem around RISC-V | Dan Robinson, The Register
Linux Foundation Europe and a number of big names in tech have banded together to drive development of a comprehensive software ecosystem that supports the open RISC-V processor instruction set…
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Semidynamics launches configurable RISC-V vector unit | Nick Flaherty, EENews Europe
Semidynamics in Spain has developed a highly configurable out of order vector unit with a new architecture to boost performance of RISC-V processor designs, and is running a demonstration of…
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Axiomise Launches Next-Generation formalISA App for RISC-V Processors
LONDON, June 01, 2023 (GLOBE NEWSWIRE) -- Axiomise, the leading provider of cutting-edge formal verification solutions that include training, consulting, services and custom apps, today launched its next-generation formalISA® app with…
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Andes Technology N25F RISC-V Processor Enables Performance and Low Power for Phison X1 Enterprise SSD Controller
Andes Technology Corp. announces that the AndesCore N25F processor has been adopted by Phison Electronics Corp.’s PCIe Gen4x4 SSD controller X1 (PS5020-E20) for the enterprise SSD market. Read the full press release.
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The Linux Foundation Europe launches RISE, the RISC-V Software Ecosystem project
The Linux Foundation Europe, the relatively new European arm of the Linux Foundation foundation of foundations, today announced the launch of the RISC-V Software Ecosystem (RISE) project. RISE aims to bring together…
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The RISE Of RISC-V: Accelerating Adoption Through Collaboration And Coordination
In an attempt to accelerate RISC-V adoption, a global consortium of industry leaders has banded together to form the RISC-V Software Ecosystem (RISE) Project. According to the project’s press release,…
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MIPS Leverages Siemens’ Veloce proFPGA platform to Implement and Make Available Capabilities of its New High-Performance eVocore P8700 RISC-V Multiprocessor
SAN JOSE, Calif., May 30, 2023 /PRNewswire/ -- MIPS, a leading developer of highly scalable RISC processor IP, has collaborated with Siemens Digital Industries Software, a global electronic design automation leader, to speed time-to-market…
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MIPS Leverages Siemens’ Veloce proFPGA platform to Implement and Make Available Capabilities of its New High-Performance eVocore P8700 RISC-V Multiprocessor
SAN JOSE, Calif., May 30, 2023 /PRNewswire/ -- MIPS, a leading developer of highly scalable RISC processor IP, has collaborated with Siemens Digital Industries Software, a global electronic design automation leader, to speed time-to-market…
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AndeSentry™ Collaborative Framework Enables Comprehensive RISC-V Security Solutions
Hsinchu, Taiwan — May 30, 2023 — Andes Technology Corporation (TWSE: 6533), a Founding and Premier member of RISC-V International and a leading provider of high-performance, low-power 32/64-bit RISC-V processors, has established AndeSentry™…
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Milk-V Surprises with a Second RISC-V SBC — Physically Compatible with the Raspberry Pi 3 Model B
RISC-V single-board computer newcomer Milk-V has announced its second hardware design, this time borrowing a very familiar form factor from a certain fruit-themed company: the credit card-sized Milk-V Mars. "Milk-V…
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Tenstorrent Partners with LG to Build AI and RISC-V Chiplets for Smart TVs of the Future
TORONTO, May 30, 2023 /PRNewswire/ -- Tenstorrent and LG Electronics Inc. (LG) are pleased to announce that they are collaborating to build a new generation of RISC-V, AI, and video codec chiplets to potentially…
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SiFive Announces Exclusive China Event Series
It is an exciting time for SiFive in China and we’re going to be talking about a future powered by our RISC-V solutions at SiFive Days, three informative events in…
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Axelera AI increases its Series A funding round to $50m for RISC-V edge AI chip
Dutch startup Axelera AI has raised $50m for its in-memory computing, RISC-V-based edge AI technology and set up a Silicon Valley office. CDP Venture Capital, Verve Ventures and Fractionelera have…
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SiFive Gives WorldGuard to RISC-V International to Make this Robust Security Model More Accessible to the RISC-V Community
SANTA CLARA, Calif.--(BUSINESS WIRE)--SiFive, Inc., the pioneer and leader of RISC-V computing, today announced the company is giving the WorldGuard security model to RISC-V International, providing the RISC-V community with…
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Imagination launches IMG CXM, the smallest GPU to bring effortless user interfaces into homes
New RISC-V compatible IMG CXM cores with native support for HDR driving down costs in the DTV and wider consumer market Imagination Technologies is bringing seamless visual experiences to cost-sensitive consumer…
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Esperanto Technologies Expands Global Partner Network
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Esperanto Technologies™, the leading developer of high performance, energy-efficient artificial intelligence (AI) solutions based on the RISC-V instruction set, today announced that it is accelerating deployment of…
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Meta details its first custom RISC-V AI silicon
Meta has revealed details of the first chip it designed in house using RISC-V to run AI frameworks for its Facebook and Instagram services. The company found that GPUs were…
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Ubuntu on VisionFive 2 RISC-V single board computer
Canonical published the optimised Ubuntu release for StarFive’s VisionFive 2, the world’s first high-performance RISC-V single board computer (SBC) with an integrated GPU. Read the full article.
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Milk-V’s Pioneer Is a Tall Glass of Cold RISC-V with 64 Cores, Up to 128GB of RAM
Chinese hardware company Milk-V Technology is preparing to launch a high-performance RISC-V computer with a difference: the Pioneer packs in 64 physical cores and supports up to 128GB of RAM…
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MTIA v1: Meta’s first-generation AI inference accelerator
AI workloads are ubiquitous at Meta — forming the basis for a wide range of use cases, including content understanding, Feeds, generative AI, and ads ranking. These workloads run on PyTorch with…
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China’s semiconductor developers eye shift to RISC-V architecture amid growing chip demand in cars, data centres and AI, executive says
China’s growing demand for semiconductors used in electric vehicles, high-end servers in data centres and artificial intelligence applications provides a vast opportunity for RISC-V processors to flourish, according to a proponent of the open-source, royalty-free chip design, even as…
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Yunhao Zhang’s Egos-2000 Packs an Entire RISC-V Operating System Into Just 2,000 Lines of Code
Software engineer and Cornell PhD candidate Yunhao Zhang has developed an operating system with a difference: packing its features into just 2,000 lines of code, egos-2000 aims to offer an…
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India’s RISC-V startup InCore receives funding from Sequoia Capital
India-based RISC-V fabless chip startup InCore Semiconductors received funding from Sequoia Capital India, the second deal that the venture capital firm invested in India's semiconductor startup. Read the full article…
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Andes Technology Announces The New Product Line, AndesAIRE™, Ultimately Efficient AI/ML Solutions For Edge And End-Point Inference
HSINCHU, TAIWAN — May 15, 2023 — Andes Technology (TWSE:6533), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced the launch…
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Yunhao Zhang’s Egos-2000 Packs an Entire RISC-V Operating System Into Just 2,000 Lines of Code
Software engineer and Cornell PhD candidate Yunhao Zhang has developed an operating system with a difference: packing its features into just 2,000 lines of code, egos-2000 aims to offer an…
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“Risc” V Opportunity: How The Custom Silicon Wave Will Benefit India’s Semiconductor Ambitions
"We believe that India will become a global semiconductor leader by 2035, with many large companies in key industry segments, such as core IP and fabless chip design." Read the…
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Esperanto Sees A Bright Future For RISC-V In AI And HPC
The company is shipping its first-gen chip globally, with over 1000 cores at only 25 watts of power. Can it break into Generative AI? Read the full article here.
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Ubuntu Now Available on the World’s First High-Performance RISC-V SBC with GPU
StarFive VisionFive 2 can now benefit from the latest and greatest Ubuntu release, improving RISC-V board experiences. Read the full article.
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Canonical enables Ubuntu on StarFive’s VisionFive 2 RISC-V single board computer
May 11, 2023 -- Canonical published the optimized Ubuntu release for StarFive’s VisionFive 2, the world’s first high-performance RISC-V single board computer (SBC) with an integrated GPU. Read the full article.
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Compiler test update boosts Andes RISC-V in automotive
Andes Technology has upgraded its version of the SuperTest Compiler Test and Validation Suite developed and supplied by Solid Sands in the Netherlands to support its growth in automotive chip…
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Art Swift, President and CEO of Esperanto Technologies, on RISC-V, HPC, AI, and Generative AI.
Karl interviews Art Swift, President and CEO of Esperanto Technologies. The company is now shipping a RISC-V SoC with over 1000 cores that consumes only 20 watts. Art talks about…
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Launch of the New Horizon Europe Project SYCLOPS
8 leading European organisations join forces to bring together RISC-V and SYCL standards to demonstrate ground-breaking advances in scalability of extreme data analytics via fully-open AI acceleration. Read the full…
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Sipeed Teases a $40 Single-Board Computer with Fully-Ratified RISC-V Vector Extensions
Sipeed has posted images teasing a new single-board computer based on a RISC-V processor boasting the ratified RISC-V Vector Extension 1.0 — something which should give a considerable boost to…
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[PODCAST] Memory Allocation, Digital-Friendly Analog and Configurable 64-bit RISC-V
In this edition of Embedded Edge with Nitin, there’s a bit of a RISC-V theme: I talk to SemiDynamics, a configurable 64-bit RISC-V startup coming out of stealth; then to…
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RISC-V ratifies compressed instruction extensions
RISC-V has ratified its extensions for code compression to reduce the memory requirements when using the open instruction set architecture. This is particularly important for microcontrollers that have limited memory…
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Tenstorrent Selects Arteris IP for HPC RISC-V Chiplets
CAMPBELL, Calif. – May 2, 2023 – Arteris, Inc. (Nasdaq: AIP), a provider of system IP designed to accelerate system-on-chip (SoC) creation, today announced that Tenstorrent, the Toronto-based AI chip…
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Charles Lohr Turns a $0.10 RISC-V Microcontroller Into a “Software-Defined Flyback” for Nixie Tubes
YouTuber Charles Lohr has come up with a novel and low-cost way to drive Nixie display tubes, turning an ultra-low-cost RISC-V microcontroller into what he describes as a "software-defined flyback…
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Tenstorrent Selects Arteris IP for AI HPC and Datacenter RISC-V Chiplets
CAMPBELL, Calif., May 2, 2023 — Arteris, Inc., a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced Tenstorrent has licensed Ncore and FlexNoC interconnect IP for…
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Menta, Codasip join RISC-V 3D neuromorphic AI project
The research wing of European RISC-V processor core developer Codasip and French embedded FPGA firm Menta have joined a project to build a 3D neuromorphic AI chip. Read the full…
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Making Developers the Protagonists: 2023 RT-Thread Global Tech Conference Registration Opens.
The RT-Thread Global Tech Conference (RGTC) is an annual event that brings together developers from around the world to focus on the latest developments in RT-Thread basic software technology and…
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RISC-V: Dividing efficiently across different hardware
Author: Paul Curtis In previous blog posts I have described the division algorithms SEGGER implemented in emRun. However, which algorithm is best (in terms of code size, execution speed, or…
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Esperanto runs generative-AI on RISC-V
Esperanto Technologies Inc. (Mountain View, Calif.) has announced it has ported a range of generative AI models to its RISC-V hardware. Initial work includes running a range of large language…
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Esperanto Technologies Announces RISC-V Industry Milestone of Generative AI Models Running on ET-SoC-1; Access to be Made Available to the RISC-V Research Community
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Esperanto Technologies™, the leading developer of high performance, energy-efficient artificial intelligence solutions based on the RISC-V instruction set, today announced that it has ported and is running…
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Secure RISC-V accelerator startup VyperCore raises £4 million
VyperCore Ltd. (Bristol, England), a startup with plans to develop novel processor technology, has raised £4 million (about US$5 million) in seed funding. The company was founded by Ed Nutting,…
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Esperanto Technologies Announces RISC-V Industry Milestone of Generative AI Models Running on ET-SoC-1; Access to be Made Available to the RISC-V Research Community
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Esperanto Technologies™, the leading developer of high performance, energy-efficient artificial intelligence solutions based on the RISC-V instruction set, today announced that it has ported and is running…
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Semidynamics Unveils First Customizable RISC-V Cores for End Users
At its heart, the RISC-V movement centers around the idea of democratizing processor design. With an open-source instruction set architecture (ISA) and a plethora of resources available to anyone free of…
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Spanish startup performs RISC-V open core surgery
Spanish startup SemiDynamics has developed fully configurable 64bit RISC-V processor IP for high-performance chip designs in AI, Machine Learning (ML) and High-Performance Computing (HPC). The customisable cores are process agnostic…
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Process agnostic fully customisable RISC-V IP cores
Semidynamics has announced the first, fully customisable, 64-bit RISC-V family of cores that are ideal for handling large amounts of data for applications such as AI, Machine Learning (ML) and…
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10 Breakthrough Technologies That Will Profoundly Affect Our Lives
Advances in technology will continue to affect our lives in myriad ways. Technology Review magazine recently picked ten of the potentially most important ones. Let's see what we have to…
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PINE64 Star64: New single-board computer orderable with RISC-V processor
PINE64, which recently introduced the PineTab2 and PineTab-V, has started selling a new RISC-V-based single-board computer (SBC). Announced last year, the Star64 relies on the StarFive JH7110 SoC, which PINE64 says should match…
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India RISC-V gets lift from Tenstorrent JV with Bodhi Computing
India received a boost to its RISC-V program this week as Tenstorrent announced its investment in and partnership with Bodhi Computing, a company set up last month by ex-Intel engineers…
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Taking control of data centres is a low-RISC move
In the early 1990s, each passing year seemed to bring a new CPU architecture. Exotic chips such as Hobbit, PA-RISC, MIPS, Sparc, PowerPC and Alpha were all ready to steal…
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Star64 Is Now Available to Order as PINE64’s First RISC-V SBC
Star64, PINE64’s first RISC-V single-board computer (SBC), is now available to order in two variants with 4GB and 8GB RAM and some impressive specs. Powered by the StarFive JH7110 Quad-Core SiFive RISC-V U74 64-bit…
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Tenstorrent Announces Strategic RISC-V Ecosystem Development Partnership with Bodhi Computing Bodhi Computing
BENGALURU, India, April 5, 2023 /PRNewswire/ -- Tenstorrent is excited to announce its continued commitment to India's Digital India RISC-V Program with its investment in and partnership with Bodhi Computing. Bodhi Computing builds and sells server-grade…
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Renesas launches RISC-V voice recognition chip
Renesas Electronics has developed its first RISC-V microcontroller designed for voice recognition interfaces systems using IP from Andes. The R9A06G150 32bit application specific processor (ASSP) provides a complete, cost-effective, production-ready voice-control…
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LLVM 17 Lands Initial Support For RISC-V Vector Crypto Extension ISA
Merged this weekend to the LLVM 17 development code-base is initial support for RISC-V's vector crypto extension ISA. The latest LLVM (17) Git code has initial support for the v0.3…
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Embedded World 2023: It’s Time To Architect All Ambitions With Custom Compute
As soon as we arrived in Nuremberg, we could feel the city was buzzing and ready for a great Embedded World 2023 conference. It was hard to avoid exhibitors, speakers, and…
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RISC-V Disrupting EDA
The electronic design automation (EDA) industry started in the 1980s and primarily was driven by the test and PCB industries. The test industry was focused on simulation so that test…
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Tenstorrent Opens Office In Japan To Capitalize On RISC-V + AI
Tenstorrent, the Toronto-based semiconductor company, now led by the super-star chip designer Jim Keller, has just opened a new office in Japan. So, as many other AI startups are struggling, Tenstorrent…
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ASUS Unveils The Tinker V As Their First RISC-V Board
For over a half-decade ASUS has been selling the Thinker Board devices as their line of Raspberry Pi alternatives. To date the ASUS Tinker Board single board computers have all been Arm-based…
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Asus Tinker Board V is the first one with 64-bit RISC-V processor
Asus' Tinker Board lineup has been around for quite some time but now, we have the first one that will be using a RISC-V processor, the Asus Tinker V. Asus'…
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Chip Industry’s Technical Paper Roundup: Mar. 14
RISC-V virtualization; hexagonal boron nitride for enhanced graphene device array; human–machine collaboration for improving process development; NIST HW-based confidential computing; ferroelectric HEMT; SpGEMM with RISC-V vector instructions; wafer defects; reducing…
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Imperas in RISC-V three way deal
Imperas Software has signed a three-way collaboration with MIPS and Ashling across all aspects of RISC-V software development. Read the full article.
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Trio support RISC-V development from SoC concept to deployment
Imperas Software has announced with MIPS and Ashling a new 3-way collaboration to support developers across all aspects of RISC-V software development for advanced processor applications. Based on the Imperas…
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Imperas Collaborates with MIPS and Ashling to Accelerate RISC-V Application Software Development from SoC Concept to Deployment
Oxford, United Kingdom – March 13th, 2023 – Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced with MIPS and Ashling a new 3-way collaboration to support developers across…
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Canonical enables Ubuntu on Microchip’s PolarFire® SoC FPGA Icicle Kit RISC-V board
March 8, 2023: Canonical published the optimised Ubuntu release for the first RISC-V based SoC FPGA – Microchip’s PolarFire® SoC FPGA Icicle Kit, expanding support for the RISC-V open source community. Read the…
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Ubuntu Now Officially Supports Microchip’s PolarFire SoC FPGA Icicle Kit RISC-V Board
Canonical announced today the general availability of official Ubuntu images optimized for Microchip’s PolarFire SoC FPGA Icicle Kit RISC-V development board. Canonical continues to expand its RISC-V offering with a new Ubuntu…
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China accelerates drive for scientific self-sufficiency
The full session of China's National People’s Congress – the annual meeting of the nation's supreme legislative body – has seen officials announce accelerated plans to achieve scientific self-sufficiency. Legislators…
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Bluespec collaborates with Synopsys to address growing verification demands for RISC-V design community |
Industry-leading Synopsys VCS simulation and Verdi hardware/software debug solutions accelerate verification and validation of RISC-V cores. Bluespec Inc., announced today a collaboration with Synopsys to provide Synopsys reference methodologies for…
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Alibaba’s T-Head foresees RISC-V to support more advanced scenarios in China
Alibaba’s chip unit T-Head said it foresees RISC-V, an open-sourced architecture for computer processors, to be used in more advanced scenarios in China. RISC-V has already been used in less-demand…
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CAST Enhances RISC-V Processor Line for Low-Power and Functional Safety Applications
Woodcliff Lake, New Jersey — March 3, 2023 — Semiconductor intellectual property provider CAST today announced the immediate availability of a new deeply embedded, low-power RISC-V processor IP core and enhancements to…
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CAST Enhances RISC-V Processor Line for Low-Power and Functional Safety Applications
Woodcliff Lake, New Jersey — March 3, 2023 Introducing a new, faster low-power embedded processor and upgrades to the current Functional Safety processor Semiconductor intellectual property provider CAST today…
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Alibaba and Ant venture to launch RISC-V chips for payments
SHANGHAI, March 2 (Reuters) - Alibaba Group Holding's (9988.HK) chip unit T-Head and Alipay, the payment service under Alibaba's financial affiliate Ant Group, will release computing chips for secure payments based on…
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Arteris and SiFive Partner to Accelerate RISC-V SoC Design of Edge AI Applications
CAMPBELL, Calif. and SANTA CLARA, Calif., Feb. 27, 2023 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, and SiFive, Inc.,…
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Imperas Collaborates with Synopsys on SystemVerilog based RISC-V Verification
ImperasDV™ verification solutions are now certified for use with Synopsys functional simulation and debug tools with ‘lock-step-compare’ for RISC-V processor verification Read the full article.
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Semiconductor India future design vision involves Design India RISC-V and ChipIn
Delivering the inaugural address, PM Narendra Modi said that semiconductors are playing a critical role in the world today in more ways than we can imagine. We have the mission…
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Imperas Collaborates with Synopsys on SystemVerilog based RISC-V Verification
ImperasDV™ verification solutions are now certified for use with Synopsys functional simulation and debug tools with ‘lock-step-compare’ for RISC-V processor verification. Read the full press release.
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Now is the Time to Pre-order the Revolutionary Risc-v Laptops – Don’t Miss Out on This Cutting Edge Technology!
The first RISC-V laptop, known as ROMA, is powered by an unnamed quad-core processor and comes with up to 16 GB of LPDDR4X memory and up to 256 GB of…
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RISC-V With Linux 6.3 Lands Optimized String Functions Via Zbb Extension
The RISC-V architecture updates were merged this Saturday for the Linux 6.3 merge window. Read the full article.
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Picocom looks to 6G with RISC-V
This year’s Mobile World Congress exhibition in Barcelona marks a key point for UK chip designer Picocom. The company, based in Bristol, UK and Shanghai, China, is exhibiting products from…
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Imperas RISC-V verification for Ventana Micro
Ventana Micro Systems is using simulation and test and verification tools from Imperas Software in the UK for the RISC-V processors under development as IP cores and chiplets for high…
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Ventana Micro Selects Imperas Solutions for RISC-V Processor Verification
Imperas RISC-V reference models, simulator, tests, and verification IP are supporting Ventana Micro in delivering a performance-leading family of data center class CPU cores. Read the full article.
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Maven Silicon’s RISC-V Processor IP Verification Flow
RISC-V is a general-purpose license-free open Instruction Set Architecture with multiple extensions. It is an ISA separated into a small base integer ISA, usable as a base for customized accelerators and…
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Ventana Micro Selects Imperas Solutions for RISC-V Processor Verification
Imperas RISC-V reference models, simulator, tests, and verification IP are supporting Ventana Micro in delivering a performance-leading family of data center class CPU cores. Read the full press release.
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MuseLab’s nanoCH32V003 Puts a 32-bit RISC-V Core on Your Breadboard for Just $1.50
The sub-10¢ microcontroller now has a $1.50 development board, though it's a bring-your-own-programmer design. Read the full article.
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Microsoft .NET Runtime Lands Initial Code For RISC-V Support
A Phoronix reader pointed out that there are initial code that landed for adding RISC-V processor support to Microsoft's .NET runtime. Read the full article.
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CH32V003 RISC-V MCU gets $1.5 development board, open source GCC toolchain and flasher utility
When we first wrote about the 10-cent CH32V003 RISC-V MCU it was offered in a $7 development board and the closed-source MounRiver Studio IDE had to be used for programming. But things…
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The nanoCH32V003 is a RISC-V dev board available for $1.50
The nanoCH32V003 is a tiny development board featuring a general-purpose 32-bit RISC-V core. Some of the peripherals found on this low-power embedded device include up to 18GPIOs, 1x USART, 1x I2C, 1x…
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Linux Kernel Address Space Layout Randomization “KASLR” For RISC-V
While there has been much work on the Linux kernel's RISC-V CPU architecture support, a feature not tackled until now has been the Kernel Address Space Layout Randomization (KASLR) support for randomizing…
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Andes and IAR Systems Together Enable Leading Vendor ILITEK to Accelerate the Development of its ISO 26262 Ready TDDI SoC ILI6600A
Hsinchu, Taiwan and Uppsala, Sweden, Feb. 14, 2023 (GLOBE NEWSWIRE) -- Andes Technology (TWSE:6533) and IAR Systems together announce that ILITEK’s Touch and Display Driver Integration (TDDI) SoC, ILI6600A, adopts the Andes…
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ChromeOS now runs on top of Linux and, er, Zephyr …
COLUMN | You probably knew Google's ChromeOS is a Linux distribution. But, now, it's running on more than Linux under the hood. I didn't, and I've been covering Chrome OS like paint since…
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IAR Unveils an Updated Brand and Name Change to Support Strategic Mission
Today, IAR launches an updated brand with a new visual identity reflecting the company’s transformational journey and focus on empowering embedded engineering. At the same time, the name changes to…
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A Closer Look at Security Verification for RISC-V Processors
Verifying the security of processors has become an essential step in the design of modern electronic systems. Users want to be sure that their consumer devices can’t be hacked, and…
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RISC-V Linux Patches Start On “zisslpcfi” Support For Control-Flow Integrity
While there is a lot to love about RISC-V, with the plethora of RISC-V extensions some of the acronyms are hard to digest. The latest example is the Linux kernel…
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Hands-on experience with StarFive VisionFive 2 RISC-V SBC using Debian 12
StarFive sent me one of their VisionFive 2 RISC-V SBC for evaluation and review. I got the model with dual Gigabit Ethernet and 8GB RAM, and I’ll report my experience with the…
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Open-Source, RISC-V Laptop Will Be Easy to Make and Upgrade
A new RISC-V concept laptop design is in the works, known as the Balthazar Personal Computing Device. This laptop design is designed from the ground up to be a completely open-source laptop,…
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Balthazar – An open-source hardware modular RISC-V, Arm, or FPGA laptop
The Balthazar Personal Computing Device (BPCD) is an open-source hardware 13.3-inch laptop with a RISC-V, Arm, or FPGA module and designed to be upgradable, expandable, and sustainable. The developers say…
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The Balthazar laptop: An all-European RISC-V Free Hardware computer
FOSDEM | The Balthazar project is designing an all-Free Hardware laptop based around RISC-V and several existing standards. Balthazar is an interesting hardware project which we were told about at the…
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Is RISC-V Ready For Supercomputing?
RISC-V processors, which until several years ago were considered auxiliary processors for specific functions, appear to be garnering support for an entirely different type of role — high-performance computing. Read…
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Xen hypervisor port to RISC-V moving – slowly, but moving
If RISC-V is to become a viable processor architecture for servers, its software ecosystem will need a solid hypervisor. Which is why The Register noted in 2021 that a project had commenced to…
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Could RISC-V become a force in high performance computing?
ANALYSIS | The RISC-V architecture looks set to become more prevalent in the high-performance computing (HPC) sector, and could even become the dominant architecture, at least according to some technical…
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Could RISC-V become a force in high performance computing?
ANALYSIS | The RISC-V architecture looks set to become more prevalent in the high-performance computing (HPC) sector, and could even become the dominant architecture, at least according to some technical…
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GreenWaves Technologies announces a €20M financing
GreenWaves, the French pioneer in RISC-V application processors for battery powered devices and a performance leader in AI and DSP, announces a 20 million euros financing led by Innovacom together…
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THE First RISC-V Shot Across The Datacenter Bow
When it comes to operating systems and now CPU instruction sets, there is proprietary, there is licensable and modifiable with a standard base of functionality with room for some originality,…
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VisionFive 2 RISC-V SBC – A Raspberry Pi Killer?
The VisionFive 2 is a quad-core RISC-V single board computer with an integrated GPU and up to 8GB of RAM. The board's biggest competitor isn't another RISC-V board but in…
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FOSDEM 2023 schedule – Open-source Embedded, Mobile, IoT, Arm, RISC-V, etc… projects
After two years of taking place exclusively online, FOSDEM 2023 is back in Brussels, Belgium with thousands expected to attend the 2023 version of the “Free and Open Source Developers’ European Meeting”…
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NASA Recruits Microchip, SiFive, and RISC-V to Develop 12-Core Processor SoC for Autonomous Space Missions
NASA’s JPL (Jet Propulsion Lab) has selected Microchip to design and manufacture the multi-core High Performance Spaceflight Computer (HPSC) microprocessor SoC based on eight RISC-V X280 cores from SiFive with…
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Espressif adopts RISC-V for next gen EPS32s, adds Wi-Fi 6 and BT 5
Espressif has used RISC-V cores in its latest ESP32 wireless microcontrollers: ESP32-C6 – ICs, modules and SDK imminent Dual RISC-V cores (160MHz + 20MHz), Wi-Fi 6 (2.4GHz), Bluetooth 5 (LE),…
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What’s next for RISC V?
First, some background. RISC V is an open-source instruction set architecture (ISA), a "free" alternative to Arm. ISAs provide a set of common, important but unglamorous "blueprints" for processors. Every processor needs…
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What Does 2023 Have In Store For Chip Design?
Predictions seem to be easier to make during times of stability, but they are no more correct than at any other period. During more turbulent times, fewer people are courageous…
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5 Takeaways From The RISC-V Summit
After an intense week at the 2022 RISC-V Summit in San Jose, California, I am fueled with energy and positive thoughts. I had plenty of time to reflect on the event, which…
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5 Takeaways From The RISC-V Summit
After an intense week at the 2022 RISC-V Summit in San Jose, California, I am fueled with energy and positive thoughts. I had plenty of time to reflect on the event, which…
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Intel & SiFive Reveal RISC-V Development Board With Quad-Core CPU Based On Intel 4 Process
Intel and RISC-V chip manufacturer, SiFive, are currently collaborating on resources to launch a development board based on the RISC-V architecture called the HiFive Pro P550, which would be based…
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Google’s Flutter showcases new graphics capabilities, WebAssembly and RISC-V support
Flutter, Google’s open-source framework for building multi-platform apps for mobile, web and desktop, is hosting its Flutter Forward event in Nairobi, Kenya today. As the name implies, the team is using the…
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These simple design rules could turn the chip industry on its head
Python, Java, C++, R. In the seven decades or so since the computer was invented, humans have devised many programming languages—largely mishmashes of English words and mathematical symbols—to command transistors…
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HiFive Pro P550 “Horse Creek” RISC-V motherboard with 16GB RAM to launch this summer
SiFive HiFive Pro P550 RISC-V motherboard based on Intel “Horse Creek” quad-core SiFive Performance P550 processor will launch this summer with 16GB DDR5 memory, two PCIe expansion slots, Gigabit Ethernet…
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Bluespec Teams Up with Synopsys for RISC-V Core Verification Effort
As the RISC-V movement gains significant traction in the industry, many engineers are finding exciting new ways of implementing the technology. Amongst these, RISC-V has become particularly popular with FPGA users, allowing for…
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The Semiconductor Shortage: How RISC-V & Other Technologies are Taking Advantage
With the semiconductor shortage showing signs of improvement, engineers now have the chance to explore new hardware platforms and alternatives. The current supply chain issues present challenges but also present…
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RISC-V Foundation’s Chairman says: “All Your Cores Are Belong to Us”
When RISC-V International’s chairman of the board Krste Asanović took the stage to report on the state of the RISC-V union at last month’s RISC-V Summit, he mouthed the phrase…
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SiFive, Intel Announce HiFive Pro P550 MicroATX RISC-V Development Board
We are now learning new details on the fruits of the partnership between SiFive and Intel. The two companies have announced that the HiFive Pro P550 development board is on track for release…
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SiFive HiFive Pro P550 dev board coming this summer with Intel “Horse Creek” RISC-V chip
Intel is best known for its x86 processors, but last year the company announced it was teaming up with RISC-V chip designed SiFive to release a “Horse Creek” development board powered by…
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HPMicro HPM64G0 – A 1 GHz RISC-V microcontroller
Yesterday, I ended up on the HPMicro website showing the illustration above about a 1 GHz MCU called HPM64G0. It looked interesting enough so I clicked on the link to a…
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Selecting The Right RISC-V Core | Brian Bailey, Semiconductor Engineering
With an increasing number of companies interested in devices based on the RISC-V ISA, and a growing number of cores, accelerators, and infrastructure components being made available, either commercially or…
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Risc-V MCUs have 8 to 20 pins
Called the CH32V003 series, they are based on the company’s own QingKe RISC-V2A core with a hardware interrupt stack and two-level interrupt nesting, supported by 16kbyte flash, 2kbyte ram and…
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Late Night Linux – Episode 212
The rise of RISC-V continues apace, we bust a recent ZFS myth, hybrid tiling in Plasma, Stadia departs with a nice gift for people, Joe draws an old skool mucky…
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Bluespec collaborates with Synopsys to address growing verification demands for RISC-V design community
Industry-leading Synopsys VCS simulation and Verdi hardware/software debug solutions accelerate verification and validation of RISC-V cores FRAMINGHAM, MASS. (PRWEB) JANUARY 11, 2023 Bluespec Inc., announced today a collaboration with Synopsys to…
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Bluespec collaborates with Synopsys to address growing verification demands for RISC-V design community
Industry-leading Synopsys VCS simulation and Verdi hardware/software debug solutions accelerate verification and validation of RISC-V cores FRAMINGHAM, MASS. (PRWEB) JANUARY 11, 2023 Bluespec Inc., announced today a collaboration with Synopsys to…
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EEVblog 1524 – The 10 CENT RISC V Processor! CH32V003
Checking out the new 10 cent WCH CH32V003 48MHz RISC V processor demo board and the MounRiver Eclipse IDE. Getting to blinky. The CH32V003 is a pin-for-pin alternative to the…
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Selecting The Right RISC-V Core
With an increasing number of companies interested in devices based on the RISC-V ISA, and a growing number of cores, accelerators, and infrastructure components being made available, either commercially or…
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$4 Sipeed M0S Dock IoT development board features BL616 WiFi 6, BLE 5.2, and Zigbee RISC-V microcontroller
As expected, Sipeed has now launched the Sipeed M0S IoT module based on Bouffalo Lab BL616 RISC-V microcontroller with 2.4 GHz WiFi 6, BLE 5.2, and Zigbee connectivity along with…
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GraalVM Native Image meets RISC-V
It is now possible to use GraalVM Native Image on RISC-V! I will explain here how to compile applications for RISC-V and the implementation. By default, Native Image uses the…
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Running Plasma on VisionFive-2
New year, new RISC-V Yocto blog post \o/ When I wrote my last post, I did really not expect my brand new VisionFive-2 board to find its way to me so soon……
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Kung-Fu Perribot with RISC-V
Kung-Fu Perribot is my newly created toy which consists of a quadrupedal robot dog with Risc-V and control of 12 Servo motors Read the full article.
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Low-cost RISC-V BL616 module supports TinyML
Sipeed launched today two embedded devices based on the RISC-V BL616 microcontroller from Bouffalo Lab. The M0S module is enabled with WiFi6, Bluetooth 5.2 and Zigbee interfaces in addition to support for DVP…
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RISC-V Bytes: Timer Interrupts
Operating systems do great work, but sometimes they need a little bit of help to know when to switch from one task to another. Thankfully, hardware is there to help!…
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Real-Time RISC-V-Based CAN-FD Bus Diagnosis Tool
Network Diagnosis Tools with industrial-grade quality are not widely available for common users such as researchers and students. This kind of tool enables users to develop Distributed Embedded Systems using…
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Andes Unveils Details of its Entry Level D23 RISC-V Processor Core
At the RISC-V Summit last month, Andes Technology announced its new D23 entry-level RISC-V processor core to the industry. At the time, there was not much truly known about the product, but recently the…
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Bluespec collaborates with Synopsys to address growing verification demands for RISC-V design community
FRAMINGHAM, MASS. (PRWEB) JANUARY 11, 2023 Bluespec Inc., announced today a collaboration with Synopsys to provide Synopsys reference methodologies for verification and hardware/software debug of RISC-V system designs with Bluespec…
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Andes Webinar 2023 | Andes President and CTO, Dr. Charlie Su, Andes Technology
Andes Webinar is the annual opportunity to get the information about RISC-V technology trends, innovative Andes solutions and more. Andes President and CTO, Dr. Charlie Su, will present a wide…
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RISC-V Reaches a Turning Point | James Sanders and Wayne Lam, CCS Insights
RISC-V, introduced in 2010, is the first novel instruction set architecture (ISA) to gain market traction in decades. New design firms such as SiFive — founded by the credited inventors…
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Removing the Risk from RISC-V using the RISC-V Trace Standard | Peter Shields, Siemens
With the growing maturity of the RISC-V ISA, chip companies now have a wealth of options for implementing RISC-V cores in their latest product. At the same time the support…
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El Correo Libre Issue 58 | Gareth Halfacree, FOSSSi Foundation
Preparations Begin for Latch-Up 2023 The FOSSi Foundation is very pleased to announce that Latch-Up will go ahead in 2023! This marks a triumphant return to in-person conferences, with Latch-Up…
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Espressif ESP32-P4 – A 400 MHz general-purpose dual-core RISC-V microcontroller | Jean-Luc Aufranc, CNX Software
Espressif ESP32-P4 is a general-purpose dual-core RISC-V microcontroller clocked at up to 400 MHz with AI instructions extension, numerous I/Os, and security features. It also happens to be the first…
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Everyone deserves a Pinecil | Chris Person, The Verge
Learning to solder was a life-changing experience for me, but it can seem daunting. You aren’t just screwing and unscrewing parts — you are melting hot metal with a scorching…
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My open source silicon highlights of 2022 and goals for 2023 | Matt Venn, Zero To ASIC Course
My favourite moments of 2022 and goals and thoughts for 2023! Watch the full video.
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My open source silicon highlights of 2022 and goals for 2023 | Matt Venn, Zero To ASIC Course
My favourite moments of 2022 and goals and thoughts for 2023! Watch the full video.
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Implementation of RISCduino core using a Hierarchical Design Flow | Dinesh Annayya, OpenRoad
Dinesh Annaya is an ardent Open-Source EDA enthusiast and an expert user of OpenROAD and OpenLane. He developed a baseline RISCduino SoC, a single, 32 bit RISC-V based controller compatible…
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MIPS Rolls Out Its First RISC-V Processor Core – It’s a Big ‘Un | Steve Leibson, EE Journal
Even though the company had telegraphed its big move, MIPS’s adoption of the RISC-V ISA for its future processor cores hit me like a ton of bricks. MIPS is one…
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A chip design that changes everything: 10 Breakthrough Technologies 2023 | Sophia Chen, MIT Technology Review
Computer chip designs are expensive and hard to license. That’s all about to change thanks to the popular open standard known as RISC-V. Ever wonder how your smartphone connects to…
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RISC-V Hibernation Support / Suspend-To-Disk Nears The Linux Kernel | Michael Larabel, Phoronix
While the open RISC-V processor architecture has proven to be highly successful, one of the features that it hasn't yet supported with the Linux kernel to this point has been…
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Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core | Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Marco Ottavi and Mauro Olivieri
Abstract: Functional safety is a key requirement in several application domains in which microprocessors are an essential part. A number of redundancy techniques have been developed with the common purpose…
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TCADer: A Tightly Coupled Accelerator Design framework for heterogeneous system with hardware/software co-design based on RISC-V | Wenqing Li, Tianyi Liu, Ziyuan Xiao HanQi, Weipu Zhu, Jian Wang
Abstract - Domain-specific architectures (DSAs) or hardware accelerators are typical innovations that are leading computer architecture into a new golden age. In a heterogeneous system, these tailored processors (accelerators) are…
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VisionFive 2: RISC-V Quad Core Low Cost SBC | Christopher Barnatt, Explaining Computers
StarFive VisionFive 2 RISC-V SBC review, including a demo of an engineering release of Debian, and of Python GPIO control. My previous “Explaining RISC-V” video is here: https://www.youtube.com/watch?v=Ps0JF... More information…
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Podcast EP135: Democratizing HPC & AI | Inspire Semiconductor, Semiwiki.com
Dan is joined by Doug Norton, VP of Business Development for Inspire Semiconductor, an Austin-based high performance computing chip design company. He is also the President of the Society of HPC Professionals,…
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Alexander Williams’ FiveForths Is a “Hand-Written” RISC-V Assembly Forth for Microcontrollers | Gareth Halfacree, Hackster.io
Written in RISC-V assembly, this tiny Forth port is open source and fully functional on the Longan Nano microcontroller. Developer Alexander Williams has written and released a "tiny hand-written" port…
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Week In Review: Design, Low Power | Marie C. Baca, Semiconductor Engineering
Top Of The News Google announced it will support the RISC-V architecture with the Android open-source operating system. In a keynote at the RISC-V Summit, Lars Bergstrom, Google’s director of engineering for the Android Platform Programming Languages,…
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MangoPi MQ-PRO Review: RISC-V Raspberry Pi Zero Alternative? | Learn Embedded Systems
In a time when Raspberry Pi’s are few and far between, alternative options such as the MangoPi MQ-PRO are increasingly interesting. In this review we cover the features, functionality and…
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Google to Make RISC-V a Major Platform for Android | Robin Mitchell, Electropages
As RISC-V continues to increase in popularity, many businesses are now turning to the processor architecture, including Google, which has just recently announced that RISC-V will become a major platform…
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How Secure Are RISC-V Chips? | Jeff Goldman, Semiconductor Engineering
Open source by itself doesn’t guarantee security. It still comes down to the fundamentals of design. When the Meltdown and Spectre vulnerabilities were first uncovered in 2018, they heralded an…
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Grokking RISC-V Vector Processing | Erik Engheim, ITNext
A friendly introduction to the core concepts in the RISC-V “V” Vector Extension, version 1.0. While the basic idea of vector processing is simple, the details can get complex. The…
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Exploring the Benefits of RISC-V ISA for Posit Arithmetic at HiPEAC Conference | Federico – The AI Blog
I am excited to announce that I will be giving a talk at the HiPEAC conference on the RISC-V ISA for posit arithmetic! HiPEAC is a leading conference in the…
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News Espressif Reveals ESP32-P4: A High-Performance MCU with Numerous IO-Connectivity and Security Features | Espressif Systems
Espressif Systems (SSE: 688018.SH) today announces the upcoming release of its latest SoC, ESP32-P4. It is powered by a dual-core RISC-V CPU with an AI instructions extension, an advanced memory…
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Ventana Introduces CES Audience to World’s Highest Performance RISC-V CPU, Veyron V1 | Ventana Micro Systems
Ventana Micro Systems announced that it will be presenting at the Consumer Electronics Show being held in Las Vegas (CES) between Jan. 5-8 the Veyron V1, the first RISC-V processor to provide performance that…
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A Bottom-Up Methodology for the Fast Assessment of CNN Mappings on Energy-Efficient Accelerators | Guillaume Devic, Gilles Sassatelli and Abdoulaye Gamatié
Abstract - The execution of machine learning (ML) algorithms on resource-constrained embedded systems is very challenging in edge computing. To address this issue, ML accelerators are among the most efficient…
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Ventana Introduces CES Audience to World’s Highest Performance RISC-V CPU, Veyron V1 | Ventana Micro Systems, Yahoo! Finance
Ventana Micro Systems Inc. announced today that it will be presenting at the Consumer Electronics Show being held in Las Vegas (CES) between Jan. 5-8 the Veyron V1, the first RISC-V processor to provide performance…
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RISC-V could become a first-class citizen for Android, Pixel 7a hands-on video leaked, and GeForce Now adds a RTX 4080 tier | Brad Linder, Liliputing
RISC-V is an open, royalty-free chip architecture positioned as an alternative to the ARM and x86 chips that dominate the PC, mobile, server, and embedded spaces. And it’s been picking…
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Breker Verification Systems Unveils Easy-To-Adopt Integrity FASTApps Targeting RISC-V Processor Core, SoC Verification Scenarios | Breker Verification Systems
Automated Test Generation Verification IP Elements Focus on Difficult Scenarios for Broad Range of Processor Cores and SoCs. Breker Verification Systems, the leading provider of advanced test content synthesis solutions,…
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Google wants RISC-V to be a “tier-1” Android architecture | Ron Amadeo, Ars Technica
Google's keynote at the RISC-V Summit promises official, polished support. Over the holiday break, the footage from the recent "RISC-V Summit" was posted for the world to see, and would you believe…
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RISC-V Summit 2022: All Your CPUs Belong to Us | Kevin Krewell, EE Times
In a recent guest editorial here on EE Times, legendary professor David Patterson wrote about busting the five myths around the RISC-V instruction set architecture (ISA). At the recent RISC-V Summit organized by RISC-V…
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Mouser Now Stocking Renesas Electronics RZ/Five-RISC-V Microprocessor for IoT Endpoint and Industrial Gateway Apps | ELE Times
Mouser Electronics, the industry’s leading New Product Introduction (NPI) distributor with the widest selection of semiconductors and electronic components, is now stocking the RZ/Five-RISC-V microprocessor (MPU) from Renesas Electronics. Expanding upon…
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RISC-V chip to drive next generation app store of hearables | Nick Flaherty, EENews Europe
US startup Sonical Sound Solutions is launching an ‘app store’ for headphones and hearables at CES this week ahead of a high performance, low power RISC-V chip. The apps run…
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What is the Titan M2 security chip in Google’s Pixel phones? | Calvin Wankhede, Android Authority
With the Pixel 6 series, Google began developing its in-house Tensor SoC. But that wasn’t the first time the search giant used a piece of custom silicon in its smartphones –…
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Arm’s push into cars ‘a logical step’ as competition grows from open-source RISC-V | Thomas Macaulay, The Next Web
Chip designer Arm is rapidly expanding its automotive business, amid mounting competition from open-source rival RISC-V. Revenue from the segment has doubled since 2020, the Financial Times reports. Dennis Laudick, VP of automotive…
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Standardized Open-Source Processor Architecture | Jon Gabay, Mouser Electronics
How often have we had to learn a new processor architecture and development environment because our new project requires more horsepower and speed than previous projects? Experience teaches us that…
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Allwinner D1/D1s Platform Support Moves Closer To Mainline Linux | Michael Larabel, Phoronix
The D1 is Allwinner's first SoC based on a RISC-V core design. While the Allwinner D1 isn't powerful at all, it's appearance in low-cost boards, RISC-V based design, and the…
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MProtect: Operating System Memory Management without Access | Caihua Li, Seung-seob Lee, Min Hong Yun, Lin Zhong
Modern operating systems (OSes) have unfettered access to application data, assuming that applications trust them. This assumption, however, is problematic under many scenarios where either the OS provider is not…
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A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance | Yuhao Ju; Jie Gu
Abstract: While neural network (NN) accelerators are being significantly developed in recent years, CPU is still essential for data management and pre-/post-processing of accelerators in a commonly used heterogeneous architecture,…
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IP-Tag: Tag-Based Runtime 3PIP Hardware Trojan Detection in SoC Platforms | Kejun Chen; Orlando Arias; Xiaolong Guo; Qingxu Deng; Yier Jin
Abstract: The complexity of modern system-on-chip (SoC) designs and the ever shortened time-to-market (TTM) makes the third-party intellectual property (3PIP) a cornerstone in the modern SoC supply chain. Various 3PIPs…
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McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework | Jianwang Zhai; Chen Bai; Binwu Zhu; Yici Cai; Qiang Zhou; Bei Yu
Abstract: Power efficiency has become a nonneglected issue of modern CPUs. Therefore, accurate and robust power models are highly demanded in academia and industry. However, it is hard for existing…
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GHAZI: An Open-Source ASIC Implementation of RISC-V based SoC | Zain Rizwan Khan, Wajeh ul Hasan, Zeeshan Rafique, Ali Ahmed Ansari, Syed Roomi Naqvi
Abstract—Due to the closed source, expensive nature of digitaldesign tools and licensing cost of System on Chip (SoC) IPsfor ASIC, the hardware industry lacks innovation and designreuse. In the last…
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How to reduce the risk when making the shift to RISC-V | Rupert Baines, Codasip
With the Intel® Pathfinder for RISC-V* program, Intel launched a development environment that enables companies of all sizes to start their RISC-V journey. Codasip makes its L31 RISC-V embedded core available to the embedded…
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From RISC-V to 3D NAND Technology—Looking Back at the Trends of 2022 | Kimber Wymore, All About Circuits
Catch up on some of the technology and industry trends we’ve noticed from 2022. This last year, 2022, has been filled with tons of new technology and events that made…
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Year 2022 in review – Top 10 posts and statistics | Jean-Luc Aufranc, CNX Software
It’s the last day of the year and the time to look at some of the highlights of 2022, some traffic statistics from CNX Software website, and speculate on what…
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RISC-V on the Final Frontier | Embedded Computing Design Staff, Embedded Computing Design
On this Episode of Embedded Insiders we’re joined by Founder and CTO of Croquet, David Smith, to discuss the company’s Portals technology which is designed to securely connect 3D, web-based spaces where…
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Bouffalo Lab BL616/BL618 RISC-V MCU supports WiFi 6, Bluetooth 5.2, and Zigbee | Jean-Luc Aufranc, CNX Software
Bouffalo Lab BL616/BL618 is a 32-bit RISC-V wireless microcontroller with support for 2.4 GHz WiFi 6, Bluetooth 5.2 dual-mode, and an 802.15.4 radio for Zigbee, Thread, and Matter designed for…
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Lichee RV 86 Panel Getting Started Guide | James A. Chambers, Legendary Technology Blog
The Lichee RV 86 Panel is a RISC-V powered Linux computer complete with screen! It comes as a low cost kit with everything you need including the Lichee RV module.…
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BSC Develops 4 Open-Source Hardware Components Based on RISC-V | HPC Wire
Greater performance demands of safety-critical, real-time systems require hardware and software components that can integrate the complexity required while adhering to stringent safety verification processes. With the EU-funded SELENE project, BSC researchers have risen…
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Tencent joins open-source chip design community RISC-V as China seeks to mitigate impact from US sanctions | Che Pan, South China Morning Post
Tencent Holdings is the latest Chinese tech firm to join RISC-V International, the world’s largest open-source processor architecture group, as China faces growing US exports restrictions in semiconductor technologies. The…
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Adapting To Broad Shifts Essential In 2022 | Brian Bailey, Semiconductor Engineering
Every year holds a number of surprises, and change provides an opportunity to innovate and gain advantage over those who are slower to adapt. Change creates opportunity, but not every…
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RISC-V Pushes Into The Mainstream | Marie C. Baca and Ed Sperling, Semiconductor Engineering
Open-source processor cores are beginning to show up in heterogeneous SoCs and packages. RISC-V cores are beginning to show up in heterogeneous SoCs and packages, shifting from one-off standalone designs…
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Server-class RISC-V Core Unveiled by Ventana at RISC-V Summit | Aaron Carman, All About Circuits
In a bid to bring RISC-V to the high-performance, data center computing space, Ventana announced their Veyron family, a series of processors positioned to offer the flexibility needed to drive…
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Efficient Trace In RISC-V | Ed Sperling, Semiconductor Engineering
Systems with RISC-V cores often include multiple types of other processors and accelerators. Peter Shields, product manager for Tessent at Siemens Digital Industries Software, talks about what’s needed for debug…
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How RISC-V has become a viable third processor architecture | Dean Takahashi, Venture Beat
The economy and the event business aren’t strong, but the RISC-V Summit drew about 1,000 people to San Jose, California, this week to hear the latest on the open-source processor. RISC-V International CEO…
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RISC-V Adds Support For Persistent Memory Devices In Linux 6.2 | Michael Larabel, Phoronix
The RISC-V processor architecture changes were merged this week for the Linux 6.2 cycle. While RISC-V has been seeing a lot of new kernel development in recent months, for the Linux 6.2…
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Europe to Dish out €270 Million to Build RISC-V Hardware and Software | Agam Shah, HPC Wire
The European Union will release €270 million in funds as it tries to attain technology independence by building chips based on the open RISC-V instruction set architecture. The EuroHPC Joint…
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Imagination’s RISC-V gambit reaches its next level | Majeed Ahmad, EDN
Imagination Technologies, a supplier of GPUs, artificial intelligence (AI) accelerators and CPU cores, has consolidated its commitment to the rapidly expanding open-standard RISC-V ecosystem by upgrading its membership to the…
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“RISC-V is Inevitable”—A Tale of Two RISC-V Summit Keynotes | Jeff Child, All About Circuits
At the annual summit, leaders in the RISC-V community had much to say about RISC-V taking over the world. The RISC-V Summit, running from December 12 to 15 this week in…
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New CAES, IAR Systems Partnership Brings NOEL-V Support to IAR Embedded Workbench
Colorado Springs, Colo. and Stockholm, Sweden — IAR Systems, a leader in software and services for embedded development, and CAES Gaisler Products, a leader in fault-tolerant processor development, are pleased to announce a…
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Qualcomm talks up RISC-V, roasts ‘legacy architecture’ amid war with Arm | Dylan Martin, The Register
COMMENT As Qualcomm tries to fight off a lawsuit from Arm demanding Qualcomm destroy its custom cores, the Snapdragon giant has signaled it may have a bigger future with RISC-V. And…
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Solutions Disclosed at RISC-V Summit: Security, Verification, and More | Jake Hertz, All About Circuits
At this year’s RISC-V Summit, stakeholders rolled out solutions revolving around verification, security, and software-defined SoCs. This week is the annual RISC-V Summit in San Jose, CA, where many of the major…
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A Growing Ecosystem for Intel Pathfinder for RISC-V | Intel Pathfinder for RISC-V, EE Times India
Intel Pathfinder for RISC-V has launched an exciting array of new features as well as continues to grow a healthy ecosystem around the initiative. Designed for SOC architects and system…
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New Dev Platforms Bring RISC-V to the Forefront of Innovation (Part 2) | Cabe Atwell, Electronic Design
Part 2 looks at more companies that are on track to adopt the RISC-V architecture for new applications ranging from robotics to home automation. This gallery is part of TechXchange: RISC-V: The…
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Finally, A Company Shows That You Can Have A High-Performance RISC-V Solution With RAS Capabilities | Patrick Moorhead, Forbes
I will be honest with you. For years, I didn't quite understand all the attention that the RISC-V ecosystem or the solutions were getting. I saw very small CPU cores…
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Alibaba’s T-Head chip unit demonstrates Android compatibility on RISC-V chips | TechNode
T-Head, the chip unit of Chinese e-commerce giant Alibaba, demonstrated Android compatibility on its RISC-V chips on Wednesday at its RISC-V Summit 2022 event. Running natively on T-Head’s prototype chipset…
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Sokol Flex OS supports RISC-V | David Manners, Electronics Weekly
Siemens Digital Industries Software says its Sokol Flex OS software now supports RISC-V embedded development with the availability of one of the industry’s first commercially supported, extensible, and customisable Linux…
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Sipeed Teases a RISC-V System-on-Module That “Beats the Raspberry Pi 4” in Performance | Gareth Halfacree, Hackster.io
With four RISC-V cores running at 2.5GHz and up to 16GB of RAM, the compact Lichee Module 4 A aims to outperform Raspberry Pi's best board. Embedded computing specialist Sipeed…
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Imagination extends its commitment to RISC-V with an upgrade to Premier level membership
London, England – 14th December 2022 – Imagination Technologies announces it has upgraded to the Premier RISC-V International membership level, further establishing its commitment to drive growth for the RISC-V ecosystem. At this Premier level, Shreyas…
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Siemens pioneers commercial grade Linux support for the RISC-V architecture
PLANO, TEXAS, December 12, 2022 - Siemens Digital Industries Software today announced that its Sokol™ Flex OS software now supports RISC-V embedded development with the availability of one of the…
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RISC-V SBC VisionFive 2 Officially Shipped
December 14, 2022 - Recently, StarFive Technology has completed production and testing of the first batch of VisionFive 2 SBCs, which has started shipment and will be delivered to customers…
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CHIPS Alliance Welcomes the Caliptra Open Source Root of Trust Project
SAN FRANCISCO, December 13, 2022 – CHIPS Alliance, a Linux Foundation project and leading consortium advancing common and open hardware for interfaces, processors and systems, announced that Caliptra, the open source root…
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Examining the Top Five Fallacies About RISC-V
In a little over a decade, RISC-V has arguably become at least the third most important instruction set architecture (ISA) for future applications of computing. In the next few years,…
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Ventana Introduces Veyron, World’s First Data Center Class RISC-V CPU Product Family
CUPERTINO, Calif. – December 13, 2022 – Ventana Micro Systems Inc. today announced its Veyron family of high performance RISC-V processors. The Veyron V1 is the first member of the…
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Ashling announce availability of their new Vitra-XS Debug & Trace Probe
Dec-12, 2022 RISC-V Summit, San Jose, Silicon Valley, California, USA - Today Ashling announced availability of Vitra-XS their newest member of the Ashling probe family. Vitra-XS is a debug &…
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XMOS Announces Software-defined SoC Platform Now Compatible with RISC-V
Bristol, UK – December, 12 2022 – XMOS today reveals a RISC-V compatible architecture for the fourth generation of its xcore platform. The collaboration delivers the flexibility to define entire systems…
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Codasip Launches SecuRISC5 initiative
Munich, Germany – December 12, 2022 – Codasip, the leader in processor design automation and RISC-V processor IP, today launched SecuRISC5, a Codasip initiative to provide its customers with safe…
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Imperas releases new updates, test suites, and functional coverage library to support the rapid growth in RISC-V Verification
Oxford, United Kingdom – December 12th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates to ImperasDV to support the rapid growth in RISC-V verification…
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Microchip Showcases RISC-V-Based FPGA and Space-Compute Solutions at RISC-V Summit
CHANDLER, Ariz. – December 8, 2022 – Mid-range FPGAs and System-on-Chip (SoC) FPGAs have played a major role in moving computer workloads to the network edge. Microchip Technology (Nasdaq: MCHP) has helped fuel…
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Imperas and Imagination Collaborate on Providing Virtual Platform Models for the Catapult RISC-V CPU Family
Oxford, United Kingdom – December 8th, 2022 – Imperas Software Ltd.,the leader in RISC-V simulation solutions, today announced that Imagination Technologies, a global technology leader in silicon IP (intellectual property), has approved the…
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Codasip Launches Codasip Labs to Accelerate Advanced Technologies
Munich, Germany – December 7, 2022 – Codasip, the leader in processor design automation and RISC-V processor IP, today announced the establishment of Codasip Labs as an innovation hub within the…
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Andes Announces RISC-V Multicore 1024-Bit Vector Processor: AX45MPV
SAN JOSE, CA – December 7, 2022 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V…
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Andes Technology Unveils The AndesCore™ D23, A Feature-Rich, Low-Power And Highly-Secured Entry-Level RISC-V Processor
SAN JOSE, CA - December 7, 2022 - Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V…
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Join Andes At RISC-V Summit; Learn The Only ISO 26262 Fully-Compliant RISC-V CPU, The Latest Multicore 4-Way Out-Of-Order Processor & The Multicore 1024-Bit Vector Processor
SAN JOSE, CA – December 7, 2022 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V…
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Andes Technology And Parasoft Collaborate To Provide Seamless Software Testing Tools For Automotive Functional Safety Applications
SAN JOSE, CA - December 7, 2022 - Andes Technology, a leading supplier of high-performance, low-power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, and Parasoft, a global…
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MIPS Selects Imperas for Advanced Verification of High-Performance RISC-V Application-class Processors
Oxford, United Kingdom – December 7th, 2022 – Imperas Software Ltd.,the leader in RISC-V simulation solutions, announced today that MIPS, a leading developer of highly scalable RISC processor IP, has selected Imperas…
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Standard Library Expertise at the RISC-V Summit Presented by Solid Sands
Amsterdam, The Netherlands – December 6, 2022 – Solid Sands, the world-leading provider of testing and qualification technology for compilers and libraries, will share its knowledge of how to qualify C…
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RISC-V: An Open-Source Churn In Computational Hardware Electronics – Part 2 | Dr Santhosh Onkar, Swarajya
The previous article was a ‘look back’ at the computation paradigm and the context in which RISC-V has emerged as a new player. In this article, we ‘look sideways’ and in the…
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Imperas and Andes collaborate to support RISC-V innovations | Andes Technology and Imperas Software
Imperas reference models for Andes expanded with Andes Custom Extension™ support and design flow integration for leading EDA environments, plus new AndesCore® N25F-SE core for functional safety applications. Imperas Software…
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UniHiker education platform teaches STEM with Mind+ and Jupyter (in China) | Jean-Luc Aufranc, CNX Software
DFRobot UniHiker is a STEM education platform with a 2.8-inch touchscreen display, a Rockchip RK3308 quad-core Cortex-A35 processor, a GD32V RISC-V microcontroller, WiFi and Bluetooth connectivity, as well as various…
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CEVA joins Intel Pathfinder for RISC-V programme | CEVA, New Electronics
CEVA, a licensor of wireless connectivity and smart sensing technologies, is to make its CEVA-BX1 and CEVA-BX2 Audio DSPs and audio front-end software stack available for commercial developers through the…
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Sipeed M1s DOCK is a tiny RISC-V dev board for $11 | Brad Linder, Liliputing
Disclosure: Some links on this page are monetized by the Skimlinks, Amazon, Rakuten Advertising, and eBay, affiliate programs. All prices are subject to change, and this article only reflects the prices available at time…
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$10.80 RISC-V AIoT module supports Linux | Giorgio Mendoza, Linux Gizmos
The Sipeed M1s is a compact module integrating the Bouffalo Lab BL808 RISC-V SoC module along with a NPU. The device also provides WiFi/BL, 802.15.4 Zigbee connectivity and support for interfaces such…
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Codasip and Intel bring RISC-V development to higher-education | Codasip
The Codasip University Program joins Intel® Pathfinder For RISC-V Codasip, the leader in processor design automation and RISC-V processor IP, today announced it is collaborating with Intel® to enable undergraduate…
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Simon Davidmann President & CEO of Imperas Software elected as Chair of the OpenHW Verification Task Group
Oxford, United Kingdom – December 5th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Simon Davidmann has been elected as Chair of the OpenHW Verification Task Group…
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Solid Sands Announces Major New Enhancements to SuperGuard
Amsterdam, The Netherlands – December 2, 2022 – Solid Sands, the world-leading provider of testing and qualification technology for compilers and libraries, announces a major new update to SuperGuard, the world’s…
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Imperas RISC-V Summit Kickoff Party, December 12 2022
Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced the Imperas RISC-V Summit Kickoff Party 2022. Start off the RISC-V Summit right, with a night of…
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CAES Design Win of RISC-V/NOEL-V IP for Idaho Scientific Secure Processor for US Critical Infrastructure
CAES, a leader in advanced mission-critical electronics for aerospace and defense, announced that it has won its first commercial U.S.-based license for its RISC-V/NOEL-V processor IP with Idaho Scientific, based in Boise, Idaho.…
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Imperas and Andes collaborate to support RISC-V innovations
Oxford, United Kingdom – November 29th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Andes Technology Corp., a leading supplier of performance-efficient and extensible 32/64-bit RISC-V processor cores…
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Cortus announces two new RISC-V microcontrollers (MCUs) Lotus family
Montpellier, France – November 28, 2022 – Cortus, an innovative French fabless semiconductor manufacturing group today announces two new RISC-V microcontrollers (MCUs). They are designed for ease of use, and…
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11 Myths About Using Formal Verification
Axiomise’s Dr. Ashish Darbari dispels a host of myths to highlight the advantages of formal verification for IC design. What you’ll learn: How formal verification is able to find bugs…
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NASA Uses RISC-V Vector Spec to Soup Up Space Computers | Chenny Wang, EE Times
With the growing demand for applications that require multiple cores and AI, ML, and computer vision capabilities, faster and power-efficient processing is essential. At the same time, companies are looking…
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Secure-IC acquires Silex Insight’s security business to accelerate its chip-to-cloud plan and develop the next-generation of embedded cybersecurity solutions
The RISC-V member @Secure-IC has announce the acquisition of @Silex Insight security business (also a RISC-V member) to accelerate its Chip-To-Cloud plan and develop the next-generation of embedded cybersecurity solutions…
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RISC-V Is Thriving: Here’s What You Need To Know | Steve Brown, Semiconductor Engineering
RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley developers in 2010, is going from strength to strength. The RISC in RISC-V stands for Reduced Instruction Set Computer,…
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SiFive launches Performance P670 and P470 RISC-V energy efficient processors | Bogdan Solca, Notebook Check
With the release of the P670 and P470 RISC-V processors, SiFive plans to deliver competitive alternatives to legacy technologies for the wearables, smart home and AR/VR markets. The new processors…
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Codasip, SiliconArts team on RISC-V ray tracing graphics IP | Nick Flaherty, EE News Europe
A high end ray tracing graphics core is shipping with a customisable RISC-V core from German developer Codasip as the first step to integrated low power AR chips. SiliconArts in…
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SEGGER introduces streaming trace probe for SiFive RISC-V cores | SEGGER
SEGGER’s J-Trace PRO with streaming trace, Live Code Profiling, and Live Code Coverage now supports all E-Series SiFive RISC-V cores with the BTM trace module. J-Trace PRO RISC-V, with its SuperSpeed USB 3.0 interface, enables…
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Open source TileLink to AHB bridges with dedicated Cocotb extensions | Antmicro
Antmicro uses open source to introduce pragmatic innovation into areas which have traditionally been heavily reliant on proprietary technologies such as ASIC and FPGA. Due to high complexity and long…
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Lilbits: RISC-V and de-Googled phones, and Qualcomm sees 2024 as the year of the Snapdragon-powered PC | Brad Linder, Liliputing
Microsoft’s new Windows Dev Kit 2023 is a $600 mini PC with 32GB of RAM, a 512GB PCIe NVMe SSD, and the most powerful Qualcomm Snapdragon processor to date… but it’s still not…
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Andes unveils AndesCore AX65 Out-of-Order RISC-V core for compute intensive applications | Jean-Luc Aufranc, CNX Software
Andes Technology has unveiled the high-end AndesCore AX60 series out-of-order 64-bit RISC-V processors at the Linley Fall Processor Conference 2022 with the new cores designed for compute-intensive applications such as…
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Android Open Source Project ports to RISC-V | Nick Flaherty, EE News Europe
The Android Open Source Project (AOSP) has been ported to the RISC-V processor architecture in a key move for the technology. Upstream enablement of RISC-V has started within AOSP which…
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SiFive P670 and P470 RISC-V processors feature RISC-V Vector Extensions | Jean-Luc Aufranc, CNX Software
SiFive has announced two new RISC-V Performance cores with the P670 and P470 processors with RISC-V Vector Extension for AI/ML, media and sensor processing, and designed for high volume applications…
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With its New RISC-V Processors, SiFive Bets on Compute Density | Jeff Child, All About Circuits
Aiming to usurp Arm processors in size-constrained, compute hungry designs like wearables, SiFive has expanded its RISC-V “Performance” line of processors. The momentum for RISC-V continues to grow, as a…
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SiFive Reveals New RISC-V Chips, the P670 and P470 | Ian Evenden, Tom’s Hardware
SiFive announced a pair(opens in new tab) of new high-performance RISC-V(opens in new tab) processors aimed at what it calls "next-generation wearables and smart consumer devices." Known as the P670 and P470, the processors…
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T-Head XuanTie C908 RISC-V core targets AIoT applications | Jean-Luc Aufranc, CNX Software
We’ve seen two announcements of high-end RISC-V cores this week with the SiFive P670 and Andes AX65 processors each with a 4-way out-of-order pipeline, but Alibaba’s T-Head Semiconductor Xuantie C908 is a little different…
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DongshanPI-D1s is a RISC-V Development Board for Less Than $20 | Ian Evenden, Tom’s Hardware
Another RISC-V development system has become available — this time with an Allwinner D1s processor on board in a package designed to teach programming. The DongshanPI-D1s, brought to our attention by CNX-Software(opens in…
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DongshanPI-D1s – An Allwinner D1s RISC-V development board designed to teach programming | Jean-Luc Aufranc, CNX Software
The DongshanPI-D1s development board is comprised of a soldered-on Allwinner D1s RISC-V system-on-module board (SoM) and a carrier board with two 40-pin headers and a 2.0mm dedicated header. This development…
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SiFive releases high-performance processors for small-size, high-volume applications | Judy Lin, DIGITIMES Asia
RISC-V computing startup SiFive, Inc., announced two new products that address the need for high performance and efficiency in small-size, high-volume applications like wearables, smart-home devices, industrial automation, AR/VR, and…
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High-performance RISC-V cores from SiFive | Steve Bush, Electronics Weekly
“P670 and P470 are specifically designed for the most demanding workloads for wearables and other advanced consumer applications,” said SiFive v-p Chris Jones. “We have optimised these RISC-V Vector-enabled products…
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The Android Open Source Project Is Now RISC-V Compatible | Laveesh Kocher, Open Source For You
A crucial advancement for the technology is the porting of the Android Open Source Project (AOSP) to the RISC-V processor architecture. The AOSP has begun enabling RISC-V upstream, which will…
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SiFive aims for ARM with high performance RISC-V vector cores | Nick Flaherty, EE News Europe
SiFIve has developed two families of RISC-V cores with vector processing for high volume applications such as wearables, smart home, industrial automation, AR/VR, and other consumer devices. The Performance P670…
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Ubuntu continues expanding RISC-V support – now, the $17 Sipeed LicheeRV | Tobias Mann, The Register
As progress revealed on Android port to the open ISA. Canonical has brought its Ubuntu Linux operating system to another RISC-V system: this week, Sipeed's LicheeRV single board computer. The…
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5 Good Things About RISC-V | Filip Benna, Semiconductor Engineering
A burgeoning ecosystem is driving a virtuous spiral of choice and innovation. RISC-V has been around for some time now, and if you are here it’s because you have heard…
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WCH Launches a Sub-10¢ RISC-V Microcontroller, While a $6.90 Dev Board Gets You Started | Gareth Halfacree, Hackster.io
Designed for less-computationally-demanding workloads, this 32-bit RISC-V chip is priced extremely aggressively. WCH Electronics has launched a new, low-cost RISC-V microcontroller chip running at up to 48MHz and which is…
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uConsole is a modular Arm for RISC-V handheld computer with optional 4G connectivity | Jean-Luc Aufranc
Clockwork’s uConsole is a modular handheld computer with a 5-inch display, a built-in keyboard, and based on a carrier board supporting various Arm or RISC-V modules compatible with the Raspberry…
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Ubuntu 22.10 Up And Running On The LicheeRV ~$19 RISC-V Board | Michael Larabel, Phoronix
In addition to supporting the SiFive HiFive Unmatched, Allwinner D1 Nezha, and VisionFive RISC-V board support, Canonical has formally announced Ubuntu 22.10 for the LicheeRV as a $16~19+ RISC-V board. Back in September…
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Hardware Trojan Inserted Inside A RISC-V Based Automotive Telematics Control Unit | Moschos, Athanasios, Kevin Valakuzhy, and Angelos D. Keromytis, Semiconductor Engineering
A new technical paper titled “On the Feasibility of Remotely Triggered Automotive Hardware Trojans” was written by researchers at Georgia Tech. “In this paper, we discuss how Hardware Trojans can…
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Ventana Micro Brings RISC-V Into The Data Center | Karl Freund, Forbes
Company hopes to match or even exceed x86 and Arm performance for data center infrastructure and applications. The data center is becoming more heterogeneous in terms of customized processors, accelerating…
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10 cents CH32V003 RISC-V MCU offers 2KB SRAM, 16KB flash in SOP8 to QFN20 packages | Jean-Luc Aufranc, CNX Software
WCH CH32V003 is a new ultra-cheap RISC-V microcontroller (MCU) clocked at 48 MHz with 2KB SRAM, 16KB flash, and a bunch of interfaces that sells for under 10 cents in…
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Rise of RISC-V: The computer chip design you need to know about | Stephen Vicinanza, Interesting Engineering
IE speaks to RISC-V team that has already shipped more than 10 Billion cores across the globe. The RISC-V is relatively a new chip in town (pronounced Risk Five). The process is…
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Google Announces New Open-source OS for RISC-V Chips | Darshil Patel, All About Circuits
Using a new Rust-based operating system, Google aims to secure ambient machine learning on embedded hardware. Researchers at Google recently announced a mathematically-secure platform, KataOS, optimized for embedded ML applications. The Alphabet…
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Ubuntu 22.10 Released With Improved Steam App, GNOME 43, RISC-V Support | Ian Evenden, Tom’s Hardware
Kinetic Kudu is finally here. The latest release of popular Linux distribution Ubuntu 22.10 has been announced for general release. This time there's quite a lot that’s new, including an excellent antelope-based…
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Espressif ESP8684 RISC-V WiFi & BLE MCU embeds up to 4MB flash in a 4x4mm package | Jean-Luc Aufranc, CNX Software
Espressif Systems ESP8684 is a single-core RISC-V microcontroller with 2.4 GHz WiFi 4 and Bluetooth 5.0 LE (BLE) connectivity that also integrates 1, 2, or 4MB flash into a tiny…
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Google comes up with new OS for RISC-V | Nick Farrell, Fudzilla
KataOS is more secure Search engine outfit Google has shown off its KataOS, a new secure operating system for embedded open-source RISC-V chips. Google's KataOS is written "almost entirely in…
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‘First’ RISC-V CPU certified compliant with ISO 26262 | Steve Bush, Electronics Weekly
Andes Technology has introduced safety-enhanced RISC-V CPU intellectual property, claiming it to be “the first to certified to be fully compliant with ISO 26262 functional safety standards for the development…
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Ox64 SBC powered by dual RISC-V processors | Giorgio Mendoza, Linux Gizmos
Pine64 announced a few days ago their latest SBC based on a dual-core RISC-V processor. The compact Ox64 is enabled with Wi-Fi 4.0, Zigbee BL5.0 in addition to an AI…
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Andes Announces the N25F-SE Processor, the World First RISC-V CPU IP with ISO 26262 Full Compliance | Yahoo! Finance
Systematic failures and random hardware failures can be mitigated by development process and safety designs of the safety-enhanced N25F-SE HSINCHU, TAIWAN, Oct. 17, 2022 (GLOBE NEWSWIRE) -- Andes Technology, a…
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IAR Systems’ Functional Safety Certified Development Tools for RISC-V support latest SiFive Automotive Solutions | IAR Systems
IAR Embedded Workbench for RISC-V provides full core support for the recently introduced SiFive Automotive E6-A and S7-A products Uppsala, Sweden – October 17, 2022 – IAR Systems®, the world leader…
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IAR boosts its automotive RISC-V support | Nick Flaherty, EE News Europe
IAR Systems has added support for the latest RISC-V automotive CPU IP from SiFive to its embedded tools. The IAR Embedded Workbench for RISC-V now supports the SiFive E6-A and…
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Ox64 SBC powered by dual RISC-V processors | Giorgio Mendoza, Linux Gizmos
Pine64 announced a few days ago their latest SBC based on a dual-core RISC-V processor. The compact Ox64 is enabled with Wi-Fi 4.0, Zigbee BL5.0 in addition to an AI…
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Google shows off KataOS, a secure operating system written in Rust | Liam Tung, ZDNET
Smart devices need better security and Google thinks KataOS, written in the Rust programming language, could help. Google has unveiled KataOS, an early exploration into a new secure operating system…
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IAR boosts its automotive RISC-V support | Nick Flaherty, EE News Europe
IAR Systems has added support for the latest RISC-V automotive CPU IP from SiFive to its embedded tools. The IAR Embedded Workbench for RISC-V now supports the SiFive E6-A and…
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Andes claims first RISC-V CPU IP with full ISO 26262 compliance, plans DSP version | Nick Flaherty, EE News Europe
Andes Technology has launched a safety-enhanced 32bit RISC-V CPU IP that it says is the first to be certified as fully compliant with ISO 26262 functional safety standards for the…
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What Is RISC, What Is RISC V, and How Do They Differ? | Arol Wright, Make Use Of
When talking about processors, x86 and ARM are the two terms that come up the most, especially if we're talking about recent devices. But there are many more architectures out…
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First RISC-V laptop uses Alibaba TH1520 SoC | Nitin Dahad, Embedded
Earlier this month RISC-V International announced that ROMA, claimed to be the world’s first native RISC-V development laptop, is powered by Alibaba T-Head’s TH1520 system-on-chip (SoC). The first 100 premium…
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French secure element processor uses RISC-V | Nick Flaherty, EE News Europe
French processor designer Tiempo Secure has developed secure IP based on the RISC-V open instruction set. The TESIC Secure Element IP uses the RV32IMCB 32bit RISC-V specification to adopt a…
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RISC-V Virtual Prototype | Pieper, P.; Herdt, V.; Drechsler, R., Semiconductor Engineering
A new technical paper titled “Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype” was published by researchers at DFKI GmbH and University of Bremen. Abstract…
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Intel demos “Horse Creek” developer board with SiFive RISC-V CPU, DDR5 RAM and PCIe 5.0 slot | Bogdan Solca, Notebook Check
The Horse Creek board features a SoC with 4x SiFive P550 cores manufactured on the Intel 4 production nodes. Intel integrated 8 GB of DDR5-5600 RAM as well as a…
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Andes Technology Announces Return of the Annual RISC-V CON on October 18th in the San Jose Airport DoubleTree Hotel | Andes Technology
San Jose, Oct. 10, 2022 (GLOBE NEWSWIRE) -- Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding…
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Alibaba RISC-V SoC Revealed as Processor for First RISC-V Laptop | Jake Hertz, All About Circuits
Alibaba's RISC-V SoC will power the ROMA development laptop, the industry’s first RISC-V offering. Of all the developments in the computing industry, the RISC-V movement is arguably the most considerable…
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Intel Horse Creek platform showcased with SiFive P550 RISC-V CPU, 8GB DDR5, PCIe Gen5 | Jean-Luc Aufranc, CNX Software
When SiFive introduced its Performance P550 64-bit RISC-V processor in 2021, we were told that Intel would use it in the Horse Creek platform with “leading-edge interface IP such as DDR and…
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Pine64’s RISC-V Ox64 Takes On Raspberry Pi Pico W | Ian Evenden, Tom’s Hardware
The Raspberry Pi Pico W has a new competitor in the form of Pine64’s upcoming Ox64, spotted by CNX Software(opens in new tab), which uses the increasingly popular RISC-V architecture to pack a lot…
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PINE64 Unveils the Ox64, a Low-Cost Dual-Core RISC-V Single-Board Computer with Breadboard Support | Gareth Halfacree. Hackster.io
With 64MB of RAM and up to 16MB of flash, this low-cost embedded machine features an unusual chip design. Open hardware specialist PINE64 has announced a new low-cost single-board computer…
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Pine64 Ox64 SBC to feature BL808 64-bit/32-bit RISC-V multi-protocol WiSoC with 64MB built-in RAM | Jean-Luc Aufranc, CNX Software
Pine64 Ox64 is an upcoming single board computer powered by Bouffalo Lab BL808 dual-core 64-bit/32-bit RISC-V processor with up to 64MB embedded RAM, multiple radios for WiFi 4, Bluetooth 5.0,…
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Intel’s Horse Creek dev board features SiFive P550 RISC-V processor and 8GB RAM | Brad Linder, Liliputing
The Intel “Horse Creek” developer board is compact computer board featuring 8GB of DDR5 memory, a PCIe 5.0 slot and SD card reader for storage, and support for Linux-based software.…
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It’s Time to Consider RISC-V | Rob Enderle, SD Times
Over the last months, ARM has pulled licenses from the ARM server-focused company, Nuvia, because of Qualcomm’s acquisition of that company. Then, recently, it sued Qualcomm to block the use…
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VisionFive 2 RISC-V Board Available For Pre-Order | Ian Evenden, Tom’s Hardware
With global stocks of Raspberry Pi not being so plentiful, Raspberry Pi alternatives are becoming more and more attractive to makers. StarFive’s VisionFive 2 RISC-V SBC that crowdfunded over the summer is finally available…
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China may prove Arm wrong about RISC-V’s role in the datacenter | Tobias Mann, The Register
ANALYSIS Arm might not think RISC-V is a threat to its newfound foothold in the datacenter, but growing pressure on Chinese chipmaking could ultimately change that, Forrester Research analyst Glenn O'Donnell…
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VisionFive 2 RISC-V single-board computer is up for pre-order for $56 and up | Brad Linder, Liliputing
The StarFive VisionFive 2 is a single-board computer with a quad-core RISC-V processor, an integrated GPU, an HDMI 2.0 port with support for 4K video and up to 8GB of…
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Alibaba T-Head TH1520 RISC-V processor to power the ROMA laptop | Jean-Luc Aufranc, CNX Software
The ROMA RISC-V laptop was announced this summer with an unnamed RISC-V processor with GPU and NPU. We now know it will be the Alibaba T-Head TH1520 quad-core Xuantie C910 processor clocked…
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Dev board for 32bit GigaDevice RISC-V | Steve Bush, Electronics Weekly
MikroElektronika has launched a development board for GigaDevice’s GD32VF103VBT6 32bit RISC-V microcontroller in its SiBrain format. Mikroe is the company is behind the ‘Click’ interface format and SiBrain is the…
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Linux 6.0 release – Main changes, Arm, RISC-V, and MIPS architectures | Jean-Luc Aufranc, CNX Software
So, as is hopefully clear to everybody, the major version number change is more about me running out of fingers and toes than it is about any big fundamental changes.…
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SiFive has licenses C++ library for Risc-V | Steve Bush, Electronics Weekly
IC intellectual property company SiFive has licensed Segger’s emRun++ C++ library for Risc-V, a library optimised for GCC/LLVM-based tool chains and embedded systems, based on the emRun and emFloat runtime…
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Researchers Build a RISC-V Chip That Calculates in Posits, Boosting Accuracy for ML Workloads | Gareth Halfacree, Hackster.io
Designed as an alternative to floating-point numbers, posits may prove key to boosting machine learning performance. A team of scientists at the Complutense University of Madrid has developed the first…
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Framework Based On An RISC-V Microprocessor Supporting LiM Operations | Coluccio, A.; Ieva, A.; Riente, F.; Roch, M.R.; Ottavi, M.; Vacca, M. RISC-Vlim, Semiconductor Engineering
A new technical paper titled “RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures” was published by researchers at Politecnico di Torino (Italy), Univerity of Tor Vergata (Italy), and University of Twente…
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Acceleration Robotics Partners with PlanV for a Robotics-Specific Open Source RISC-V Microcontroller | Gareth Halfacree, Hackster.io
Designed specifically for ROS 2, the roscore-v RISC-V microcontroller promises reduced latencies and new real-time capabilities. Performance-boosting specialist Acceleration Robotics has announced a partnership with Germany's PlanV, which will see…
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Google experiments with RISC-V | Nick Farrell, Fudzilla
SiFive RISC-V chips are being used by Google to run some of its AI workloads and tested in Google datacentres. SiFive's Intelligence X280 is a multi-core RISC-V design with vector extensions.…
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The Automotive Space Gears Up to Take on RISC-V | Murray Slovick, Electronic Design
SiFive is creating a lineup of compute IP for MCUs, MPUs, and soon, SoCs, as well as vector-processing solutions tailored for automotive applications. The first automotive family cores will become…
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ST to make European octacore RISC-V space chip with selectable cores | Nick Flaherty, EE News Europe
Space system designer CAES has built the first eight core fault tolerant chip that is selectable between different architectures, including RISC-V. The radiation hardened GR765 System-on-Chip (SoC) is the first user selectable…
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Arm vs RISC-V? Which One Is The Most Efficient? | Gary Explains
Arm has been making power efficient processors for decades. RISC-V is relativity new and many parts of its specifications aren't even ratified, but that hasn't stopped chip designers making RISC-V…
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Native RISC-V ROS chip targets robotics | Nick Flaherty, EE News Europe
Two European companies are developing a microcontroller chip using the open source RISC-V instruction set that is optimised to run the latest Robot Operating System (ROS2). The roscore-v project aims…
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SiFive RISC-V cores picked for Google AI compute nodes | Dan Robinson, The Register
Cor, that's a shot in the arm for this upstart CPU ISA RISC-V chip biz SiFive says its processors are being used to manage AI workloads to some degree in…
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Google deploys SiFive’s Intelligence X280 processor for AI workloads | Sebastian Moss, Data Center Dynamics
Google is using the RISC-V-based SiFive Intelligence X280 processor in combination with the Google TPU, as part of its portfolio of AI chips. Fabless chip designer SiFive said that it…
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Codasip joins OpenHW to push RISC-V verification | Nick Flaherty, EE News Europe
German RISC-V core designer Codasip has joined the OpenHW group to push for advances in the verification of RISC-V cores. Codasip has highlighted issues with verification of cores designed with…
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ARM IS THE NEW RISC/UNIX, RISC-V IS THE NEW ARM | Timothy Prickett Morgan, The Next Platform
When computer architectures change in the datacenter, the attack always comes from the bottom. And after more than a decade of sustained struggle, Arm Ltd and its platoons of licensees…
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Oracle brews Java 19. Mmmm, kinda tastes like RISC-V | Thomas Claburn, The Register
Oracle on Tuesday marked the release of Java 19 (JDK 19), the latest iteration of the popular general purpose programming language. In its evangelizing slide deck accompanying this release, Oracle…
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Renesas unveils motor control RISC-V ASSP | Gina Roos, Electronic Products
Renesas claims the industry’s first RISC-V MCU for advanced motor control, delivering a pre-programmed ASSP for a variety of applications. Renesas Electronics Corp. has claimed the industry’s first RISC-V microcontroller…
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Renesas delivers RISC-V based motor control ASSP | Nitin Dahad, Embedded.com
Pre-programmed motor control ASSP eliminates RISC-V related tools and software investment, making it easier to target applications such as home and building automation, healthcare devices, and drones. Renesas Electronics Corporation…
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SoC.one and Imagination to enable adoption of RISC-V for automotive design | Neil Tyler, New Electronics
SoC.one Inc and Imagination Technologies have formed a strategic alliance to accelerate the adoption of RISC-V in the automotive design cycle. With the electrification of cars changing how they are…
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SiFive Rolls Out Powerful New RISC-V Portfolio to Address Unmet Performance and Feature Needs of Rapidly Evolving Next-Gen Digital Automobiles | SiFive
SiFive, Inc. the founder and leader of RISC-V computing, today announced three products as part of the first phase of a long-term roadmap and portfolio designed to meet the specific needs…
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The Open Source Ztachip Is a RISC-V Accelerator for Edge AI and Computer Vision Applications | Gareth Halfacree, Hackster.io
Designed to outperform even RISC-V chips with the recently-ratified vector extensions, ztachip can boost performance by up to 50x. Embedded developer Vuong Nguyen has released an open source RISC-V accelerator…
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RISC-V Does Motor Control | William G. Wong, Electronic Design Magazine
RISC-V is a topic that garners lots of interest, but RISC-V itself is nothing more than a scalable, open-source instruction set definition. It’s the implementation that makes things interesting. Though…
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NASA Taps SiFive’s RISC-V Core for its Spaceflight Processor | Jake Hertz, All About Circuits
Responsible for inventions from wireless headphones to portable computers, space exploration has long been a field responsible for driving significant technological innovation. Today, NASA is fervently continuing this trend as the…
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Intel Shows Support for RISC-V Chip Design With Intel Pathfinder | Jake Hertz, All About Circuits
In yet another win for RISC-V, Intel has released a program to bolster the pre-silicon development of RISC-V devices. Emerging as a small project out of UC Berkeley in 2010, the…
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Dolpin Design teams for RISC-V Headphone 3.0 chips | Nick Flaherty, EE News Europe
French IP developer Dolphin Design has teamed up with Sonical in the US on the design of a platform for the next generation of chips and operating system for hearables…
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RISC-V to Launch into Space | James Morra, Electronic Design Magazine
SiFive, a startup developing IP based on the RISC-V architecture, said NASA has selected it to supply the core CPU for the agency's next high-performance spaceflight processor, a big win…
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NASA’s new space computer to be powered by custom RISC-V processor | Joel Khalili, Tech Radar
NASA pens deal with SiFive, Microchip. NASA’s new High-Performance Spaceflight Computer (HPSC) will be powered by a custom RISC-V-based processor, it has been revealed. The product of a collaboration between SiFive…
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Andes Technology Corp. Announces Its RISC-V CPU IP Serves as the Computing Engine in the New Renesas R9A02G020 MCU ASSP | Andes Technology
Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced Andes’ Entry-Level RISC-V…
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First RISC-V chip optimised for motor control | Nick Flaherty, EE News Europe
Renesas Electronics has developed the industry’s first RISC-V MCU specifically optimized for motor control systems. The R9A02G020 is a pre-programmed application specific standard product (ASSP) based on a 32bit RISC-V…
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Renesas extends RISC-V Embedded Processing portfolio | Neil Tyler, New Electronics
Renesas Electronics has introduced the industry’s first RISC-V MCU specifically optimised for advanced motor control systems. The solution provides customers with a ready-to-use, turnkey solution for motor control applications, with…
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RISC-V-Based ASSP EASY – The Start of a New Development Journey | Giancarlo Parodi, Renesas
The RISC-V instruction set architecture (ISA) is increasingly generating interest and momentum within the embedded community. The free and open RISC ISA is driven by open collaboration with the goal…
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Renesas Extends Leading RISC-V Embedded Processing Portfolio with New Motor Control ASSP Solution | Renesas
RISC-V based ASSP Offered in Collaboration with Ecosystem Partners Delivers Complete, Production-Ready Motor Control System Solution. Renesas Electronics Corporation (TSE: 6723), a premier supplier of advanced semiconductor solutions, today introduced…
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NASA, Microchip, SiFive Announces Partnership for RISC-V Spaceflight Computing Platform | Gareth Halfacree, Hackster.io
Designed to replace existing systems still using a processor design from 1997, the RISC-V-powered chip will offer 100 times the performance. NASA has confirmed a partnership with Microchip and SiFive…
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NASA has chosen these CPUs to power its next generation of spaceflight computers | Liam Tung, ZD Net
NASA selects RISC-V chip designer SiFive to help replace its aging and over-designed spaceflight computers. NASA has selected SiFive, a US chip startup that designs RISC-V CPUs, to provide the…
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Alibaba Cloud Reveals New RISC-V Development Platform | Robin Mitchell, Electropages
Recently, Chinese giant Alibaba Cloud unveiled a new RISC-V development platform that it hopes will continue to push developers into the field of RISC-V. What challenges does RISC-V currently present…
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NASA Selects SiFive and Makes RISC-V the Go-to Ecosystem for Future Space Missions | SiFive, Business Wire
SiFive X280 delivers 100x increase in computational capability with leading power efficiency, fault tolerance, and compute flexibility to propel next-generation planetary and surface missions. SiFive, Inc., the founder and leader…
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SiFive RISC-V CPU cores to power NASA’s next spaceflight computer | Tobias Mann, The Register
After more than two decades, the space agency's PowerPC love affair appears to be at an end. Chip designer SiFive said Tuesday its RISC-V-compatible CPU cores will power NASA’s just-announced…
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Four things to know about the Intel Pathfinder for RISC-V | Majeed Ahmad, EDN
As if Intel testing the RISC-V waters wasn’t news in itself, the semiconductor behemoth’s Intel Pathfinder for RISC-V initiative is now making the headlines. RISC-V is an open standard instruction…
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Intel Pathfinder for risc-v delivers new capabilities silicon development | Scientific Computing World
Intel Pathfinder for RISC-V aims to transform the way SOC architects and system software developers define new products. It allows for a variety of RISC-V cores and other IP to…
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Intel puts more weight behind RISC-V with Pathfinder platform | Nitin Dahad, Embedded.com
New Intel Pathfinder for RISC-V platform enables developers to create their own products using RISC-V cores and IP from the partner ecosystem, instantiate on FPGA and simulator platforms, and run…
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Intel leans harder on RISC-V | Chris Edwards, Engineering & Technology
No more not-invented here for the chip giant when it comes to processor architectures. Much like IBM after the PC architecture ran away from it and almost collapsed Big Blue’s…
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SoC.one Cloud Accelerates Adoption within Intel Pathfinder for RISC-V Ecosystem | SoC.one Inc.,
SoC.one Inc., a leading provider of cloud-native System on Chip (SoC) design enablement, today announced support for Intel® Pathfinder for RISC-V*, a rapid prototyping and development platform for the RISC-V ecosystem.…
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Intel launches Pathfinder development kit for RISC-V | Judy Lin, DigiTimes
Intel launched the Pathfinder development kit for RISC-V on August 30 to transform the way SOC architects and system software developers define new products. Vijay Krishnan, general manager, RISC-V Ventures…
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Andes and Green Hills Collab Yields RISC-V-based SoC for Automotive Safety | Abdulwaliy Oyekunle, All About Circuits
Manufacturers in the computing industry use RISC-V to create custom designs in RISC-V processor-based architectures. Andes Technology is one such company introducing safe and secure computing on its AndesCore 25-Series 32/64-bit CPU…
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Andes Technology Corp Announces Its Joined Intel Pathfinder | Andes Technology
Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, reveals its contribution…
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European tech in Intel’s RISC-V Pathfinder dev kit | Nick Flaherty, EE News Europe
Intel has used significant amounts of European technology in its Pathfinder RISC-V development kit. The kit allows for a variety of RISC-V cores and other IP to be instantiated on…
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PINE64 Shows Off the First Star64 RISC-V Single-Board Computer Prototypes, Targets a Launch in Weeks | Gareth Halfacree, Hackster.io
PINE64 has published the first pictures of its upcoming Star64 RISC-V single-board computer, a quad-core 64-bit Linux-capable gadget it hopes will offer competition to StarFive's crowdfunded VisionFive 2. "Just three…
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RISC-V International and Intel team up to accelerate RISC-V adoption: Introducing Intel Pathfinder for RISC-V | Intel
Founded in 2015 with only 29 members, the RISC-V Foundation, a nonprofit organization, was chartered to standardize and promote the free and open RISC-V instruction set architecture (ISA), along with its…
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Imperas partners with Intel Pathfinder for RISC-V | Imperas Software
New Integrated Development Environment for RISC-V includes Imperas simulator and reference model as a fixed platform kit for software development and architectural analysis Imperas Software Ltd., the leader in RISC-V…
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SoC.one Cloud Accelerates Adoption within Intel Pathfinder for RISC-V Ecosystem | SoC.one
SoC.one Inc., a leading provider of cloud-native System on Chip (SoC) design enablement, today announced support for Intel® Pathfinder for RISC-V*, a rapid prototyping and development platform for the RISC-V ecosystem.…
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LeapFive Eyes High-performance Realm with 1.8 GHz RISC-V SoC | Chantelle Dubois, All About Circuits
Chinese startup LeapFive recently announced the NB2 SoC, a RISC-V platform specifically designed to accelerate artificial intelligence applications (AI) with accelerated vision and audio processing capabilities. The company claims the NB2 will…
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Intel Taps MIPS eVocore for Intel Pathfinder for RISC-V | MIPS
MIPS, a leading developer of highly scalable RISC processor IP, announced it is working with Intel to accelerate innovation in open computing. As part of this effort, MIPS' eVocore is being incorporated…
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Crypto Quantique’s quantum-driven silicon IP enables root-of-trust in the Intel Pathfinder for RISC-V environment | Crypto Quantique
Crypto Quantique, a specialist in quantum-driven cyber security for the internet of things (IoT), announces that the company’s QDID silicon IP block has been selected for the recently announced Intel®…
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Intel Chooses Check Point Software Technologies to Enable Security for New Intel Pathfinder for RISC-V Platform | Check Point Software Technologies INC
Check Point® Software Technologies Ltd. (NASDAQ: CHKP), a leading provider of cyber security solutions globally, has announced a new collaboration with Intel Corporation. Check Point Quantum IoT Protect will be made available within Intel’s new…
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VisionFive 2 quad-core RISC-V dev board | Julian Horsey, Geeky Gadgets
StarFive Tech has taken to Kickstarter this month to launch their new open source quad-core RISC-V dev board in the form of the VisionFive 2. Providing developers, enthusiasts and hobbyists with a high…
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NSITEXE, OTSL, Kyoto Microcomputer, AXELL, Collaborate to develop RISC-V based Reliable Edge AI platform | NSITEXE
NSITEXE, Inc. (Head Office: Minato-ku, Tokyo, President and CEO: Yukihide Niimi, hereinafter “NSITEXE”), in collaboration with OTSL Inc. (Head Office: Nagoya, Aichi, Japan; President: Shoji Hatano, hereinafter “OTSL”), Kyoto Microcomputer…
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Lilbits: PineBuds Pro, PlayStation Studios Mobile Division, and StarFive JH7110 RISC-V chip details | Brad Linder, Liliputing
At least two upcoming single-board computers will be powered by StarFive’s new JH7110 processor featuring four RISC-V CPU cores and Imagination BXE-4-32 graphics, the Star64 board from Pine64, and the VisionFive 2 from StarFive.…
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Pine64 Star64 SBC to feature StarFive JH7110 quad-core RISC-V processor with Imagination GPU | Jean-Luc Aufranc, CNX Software
Pine64 Star64 is an upcoming single board computer (SBC) powered by StarFive JH7110 quad-core 64-bit RISC-V processor equipped with an Imagination BXE-4-32 GPU, and in a form factor similar to…
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StarFive JH7110 RISC-V processor specifications released | Jean-Luc Aufranc, CNX Software
With the Star64 and VisionFive 2 single board computers, we’ve already got two hardware platforms based on the StarFive JH7110 quad-core RISC-V processor, but somehow we did not get the detailed specifications of the…
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RISC-V pioneer raises funds for IoT, automotive | Peter Clarke, EE News Europe
Chinese RISC-V processor IP company Nuclei System Technology has raised hundreds of millions of yuan (100 million yuan is about US$15 million) in an additional funding round. The money will…
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StarFive Announced 2 High-Performance RISC-V Products: JH7110 SoC and VisionFive 2 SBC | Design and Reuse
August 23 witnessed a significant breakthrough in the RISC-V industry. StarFive, the leader of the RISC-V software and hardware ecosystem, held its 2022 online Product Announcement and unveiled two new…
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Pine64 reveals the Star64 RISC-V based Single Board Computer | Giorgio Mendoza, Linux Gizmos
Yesterday, Pine64 made an announcement about the Star64 Single Board Computer (SBC) prototype. The company mentioned this SBC will be powered with the RISC-V based StarFive JH7110 64-bit processor. The processor integrated…
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RISC-V Universe Grows with New GPUs, CPUs, and Development Kits | Abdulwaliy Oyekunle, All About Circuits
More companies continue to leverage RISC-V, a free open source instruction set architecture, to push innovation in GPUs and real-time CPU devices. As a free and open instruction set architecture…
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As Alibaba declares new RISC-V milestone, is automotive MCU the next battleground? | Misha Lu, DigiTimes
At RISC-V Summit China 2022, Alibaba Group's chip design subsidiary,T-Head Semiconductor, launched the Wujian 600 development platform based on the open-source architecture. According to the company, the development platform supports…
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Alibaba releases RISC-V development platform | Nick Farrell, Fudzilla
Edge SoCs coming Alibaba Cloud has released a development platform to help engineers building high-performance Systems-on-Chip (SoC) silicon based on the RISC-V open architecture. Alibaba Cloud wants its Wujian 600…
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Dragon Li’s Bajiu Lite Is a Flexible FPGA Development Board with RISC-V SoC Capabilities | Gareth Halfacree, Hackster.io
FPGA specialist Dragon Li Studio is looking to launch a "resource-rich" open source development board with an integrated RISC-V system-on-chip (SoC): the Bajiu Lite. "Bajiu Lite is a resource-rich FPGA…
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Pinecil V2 Review: Smart Soldering Iron, Powered by RISC-V CPU | Les Pounder, Tom’s Hardware
The humble soldering iron has come a long way. From a simple piece of hot metal which melts a mixture of tin and lead, to RISC-V powered, temperature controlled precision…
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Alibaba Cloud unveils RISC-V chip development platform | Aaron Tan, Computer Weekly
The Wujian 600 chip development platform will help developers build systems-on-chip to support edge applications such as home robots, medical imaging and video conferencing. Alibaba Cloud has unveiled a chip…
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Alibaba Cloud launches RISC-V chip-development platform | TechNode
Chinese e-commerce giant Alibaba’s cloud arm launched a new chip development platform called Wujian 600 on Wednesday. The platform was created for developers to design system-on-chips (SoCs) used for AI…
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Imagination teams for RISC-V development platform for edge AI chips | Nick Flaherty, EE Time Europe
Alibaba Cloud, the cloud business of Chinese giant Alibaba, has launched a development platform for edge AI chips based on the RISC-V open standard instruction set and IP from Imagination…
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Imagination’s GPU and AI Accelerator Licensed for the latest AIoT RISC-V-based applications | Imagination Technologies
Imagination Technologies announces that its IMG B-Series GPU and PowerVR Series3NX NNA cores have been licensed for the latest RISC-V-based SoCs of Alibaba Group’s T-Head Semiconductor for AIoT (Artificial Intelligence of Things) applications. Imagination joined the Wujian…
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Imagination’s GPU and neural processor on Alibaba Risc-V AI chip | Steve Bush, Electronics Weekly
Alibaba Group’s T-Head chip design company has adopted Imagination Technologies B-Series GPU and Series3NX neural network accelerator for an artificial intelligence IoT SoC. The Hertfordshire company joined T-Head’s ‘Wujian platform…
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Andes Technology USA Corp. to Host First Virtual Career Event Seeking RISC-V Talent to Grow Its North America Operation | Andes Technologies
Andes Technology USA Corporation, the headquarters of North America operations of Hsinchu, Taiwan-based Andes Technology Corporation, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today…
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Alibaba Cloud launches RISC-V developer platform for edge SoCs | Dan Robinson, The Register
China's Alibaba has released a development platform to help engineers building high-performance Systems-on-Chip (SoC) silicon based on the RISC-V open architecture, which is claimed to also include an optimized software…
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Chip Pioneers to Battle it out in Modern RISC-V AI Chips | Agam Shah, HPC Wire
Some chip pioneers from the 1980s are raising the ante in modern chip design with new opportunities provided by artificial intelligence and the open-source RISC-V architecture. Untether AI, which was…
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Costs Of Static HW Partitioning On RISC-V | Ralf Ramsauer, Stefan Huber, Konrad Schwarz, Jan Kiszka, Wolfgang Mauerer, Semiconductor Engineering
A new technical paper titled “Static Hardware Partitioning on RISC-V — Shortcomings, Limitations, and Prospects” was published by researchers at Technical University of Applied Sciences (Regensburg, Germany) and Siemens AG…
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Pavilion Panel: Those Darn Bugs | Axiomise
While the size of a computer shrank from a mainframe to a watch, an unquestionably remarkable feat, the time to verify these complex designs hasn’t. Neither have bug escapes, even…
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Engineering Academy Tackles RISC-V in Next Educational Event Installment | William G. Wong, Machine Design
The Sept. 8 learning event from Electronic Design will feature in-depth coverage of RISC-V architecture, hardware, software and a robust panel discussion. The open-source RISC-V instruction set architecture (ISA) has…
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LeapFive launches NB2 RISC-V flagship SoC in China | Bogdan Solca, Notebook Check
The NB2 SoC includes four RISC-V cores produced by SiFive, as well as an iGPU, NPU and VPU. LeapFive employed 12 nm nodes to produce the chips and also offers…
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Amid Chip Shortages, Companies Bet on RISC-V | Lianne Frith, All About Circuits
The RISC-V architecture continues to gather momentum as organizations make efforts to leverage the open-source ISA technology and innovate with new RISC-V solutions. Amid the chip supply issues over the…
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LeapFive NB2 is a New RISC-V Processor | Ian Evenden, Tom’s Hardware
Hardware based on the open-source RISC-V architecture keeps coming, with the latest Chinese vendor going by the name LeapFive, as spotted in the pages of CNX Software(opens in new tab). Its…
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StarFive Opens Crowdfunding for the VisionFive 2 RISC-V SBC, Starting at Just $46 | Gareth Halfacree, Hackster.io
StarFive has opened crowdfunding for its second hobbyist-focused RISC-V single-board computer (SBC), the VisionFive 2 — promising a faster device with twice the cores, a GPU, and dual gigabit Ethernet…
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1400 RISC-V cores for on-chip machine learning | Nick Flaherty, EE News Europe
Untether AI in Canada has developed a AI device with over 1400 RISC-V processors called Boqueria for ‘at memory’ computing. Boqueria, discussed at the HotChips Conference today, is built on…
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StarFive VisionFive 2 quad-core RISC-V SBC launched for $46 and up (Crowdfunding) | Jean Luc Aufranc, CNX Software
As expected, StarFive has officially unveiled the JH7110 quad-core RISC-V processor with 3D GPU and the VisionFive 2 SBC. I just did not expect the company to also launch a Kickstarter…
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Experimental Patches Allow Much Faster AArch64 & RISC-V Kexec Kernel Reboots | Michael Larabel, Phoronix
For those making use of Kexec reboots for booting to a new kernel without fully bringing down the system to reduce the server downtime from POST'ing and other hardware initialization…
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Ubuntu Announces Compatibility With Second RISC-V System | Ian Evenden, Tom’s Hardware
The popular free operating system Ubuntu will now be officially available(opens in new tab) on a second line of RISC-V single-board computers, this time the VisionFive(opens in new tab) board from Chinese manufacturer StarFive.…
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StarFive VisionFive 2 single-board PC with a quad-core RISC-V chip coming in November | Brad Linder, Liliputing
Last year Chinese company StarFive launched a compact single-board computer called the VisionFive v1 that’s powered by a 1.5 GHz dual-core RISC-V processor. Now the company has unveiled version two and it’s an upgrade…
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China’s RISC-V pioneer raises funds for IoT, automotive push | Peter Clarke, EE News
RISC-V processor IP company Nuclei System Technology Co. Ltd. (Shanghai, China) has raised hundreds of millions of yuan (100 million yuan is about US$15 million) in an additional funding round.…
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Ubuntu Now Supports The Allwinner D1 Powered Nezha RISC-V Board | Michael Larabel, Phoronix
Last week Canonical announced official Ubuntu RISC-V images for the StarFive VisionFive board while this week they are expanding their supported RISC-V line-up to also include the Nezha single board computer powered…
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LeapFive NB2 quad-core RISC-V processor comes with GPU, NPU, and DSP | Jean-Luc Aufranc, CNX Software
After SiFive and StarFive, here comes LeapFive RISC-V silicon vendor offering the NB2 quad-core 64-bit RISC-V application processor with GPU, NPU, and vision and audio DSPs capable of running Linux. LeapFive NB2…
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Implementing Cryptographic Algorithms For The RISC-V Instruction Set Architecture In Two Cases | Intel, North Arizona University and Google, Semiconductor Engineering
This new technical paper titled “Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms” was published by researchers at Intel, North Arizona University and Google, with partial funding from U.S.…
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StarFive VisionFive V1 RISC-V SBC gets Ubuntu 22.04.1 Server image from Canonical | Jean-Luc Aufranc, CNX Software
Canonical has been working on RISC-V support for Ubuntu for a while and released Ubuntu 20.04/21.04 64-bit RISC-V images for QEMU and HiFive boards last year. Now the company has released an…
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RISC-V Processor IP Provider Nuclei Technology Secures New Funding | Pandaily
Nuclei Technology, a provider of RISC-V processor IP and related overall solutions, announced on August 18 that it has completed a new round of financing totaling several hundred million yuan.…
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First RISC-V processor starts operation in orbit | Nick Flaherty, EE News Europe
The first RISC-V processor is space has started operation in a European nanosat. The Trisat-R nanosat developed by the University of Maribor in Slovenia uses a fault tolerant NOEL-V RISC-V…
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Now you can run Ubuntu on a VisionFive single-board PC with a RISC-V processor | Brad Linder, Liliputing
StarFive’s VisionFive single-board computers are compact PCs powered by RISC-V processors. Aimed at developers, the first model launched last year with a dual-core processor, while a second-gen version with a quad-core chip and…
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StarFive VisionFive V1 RISC-V SBC gets Ubuntu 22.04.1 Server image from Canonical | Jean-Luc Aufranc, CNX Software
Canonical has been working on RISC-V support for Ubuntu for a while and released Ubuntu 20.04/21.04 64-bit RISC-V images for QEMU and HiFive boards last year. Now the company has released an…
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Crypto Quantique joins RISC-V International | Nick Flaherty, EE News Europe
London-based embedded security startup Crypto Quantique has joined RISC-V International, the industry group for the open standard processor technology. “Our mission is to provide seamless end-to-end security for the IoT…
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Andes, Green Hills team for RISC-V automotive safety | Nick Flaherty, EE News Europe
Andes Technology is working with Green Hills Software (GHS) on an integrated RISC-V automotive safety platform with hardware and software. This will use the AndesCore 25-Series family of RISC-V cores…
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Andes Technology and Green Hills Software Team Up to Deliver Advanced Automotive Safety Platform for RISC-V | Andes Technologies
Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading RISC-V CPU IP vendor and a Founding and Premier member of RISC-V International, and Green Hills Software, the worldwide leader…
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Microchip to develop next generation 12 core RISC-V space processor for NASA | Nick Flaherty, EE News Europe
Microchip has won a $50m project to develop the next generation of high reliability processor for space missions based on RISC-V technology with European engineers. NASA’s Jet Propulsion Laboratory has…
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Latest Funding Drives Ventana’s First RISC-V Chiplets in Data Centers | Nitin Dahad, EE Times
Ever since Ventana Micro Systems came out of stealth last year, the company has been busily developing relationships with partners and potential customers to create traction for its RISC-V–based chiplets, which it…
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2022 RISC-V Taipei Day to be held in September to explore RISC-V driven developments in EV, smart vehicles | DigiTimes Asia
According to the semiconductor research company IC Insights, the global MCU revenue in 2022 will reach US$21.5 billion and the growth of automotive MCUs will outpace the growth of other…
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Latest Funding Drives Ventana’s First RISC-V Chiplets in Data Centers | Nitin Dahad, EE Times
Ever since Ventana Micro Systems came out of stealth last year, the company has been busily developing relationships with partners and potential customers to create traction for its RISC-V–based chiplets, which it…
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RISC-V Summit China 2022 Announces Agenda | Inside HPC
The RISC-V Summit China 2022 (Aug. 24-26) today announced its 2022 agenda, including keynotes, tutorials, and technical presentations in English language and Chinese language editions. This year’s summit includes more than 80…
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Case study: optimizing PPA with RISC-V custom extensions in TWS earbuds | John Minh, Andes Technologies
A common goal for many IC designs is achieving an optimum combination of power, performance, and area (PPA). This article examines the components and design of a currently shipping true…
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DAC – where RISC-V thrives and mixed signal design blends in | EW Staff, Electronics Weekly
At last month’s 59th DAC (Design Automation Conference), a significant announcement was made by Siemens Digital Industries Software. Acknowledging the growth of mixed signal design, and the complexities it brings,…
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