LDRA Updates Tools to Automate Worst-Case Execution Time Analysis for RISC-V
The tool suite automatically analyzes shared memory and measures worst-case execution time to ensure deterministic execution time for RISC-V processors. Developers... Read more.
Angelina Jolie Was Right About Computers
Incredibly, Angelina Jolie called it. The year was 1995. Picture Jolie, short of both hair and acting experience, as a teenage hacker in Hackers. Not a lot of... Read more.
Enhancing Commercial Software Adaptation with XuanTie Optimized Computing Libraries
By Yunfei Zhou, Alibaba DAMO Academy 1. Introduction The RISC-V architecture has matured over time. Its open, flexible, and extensible nature shows great promise... Read more.
Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms
This blog looks at the benefit of Rivos and Canonical partnering and how this partnership will impact future AI and Data Analytics use cases. Artificial intelligence... Read more.
RISC-V International at Embedded World, 11-13th March, Nuremberg Germany
embedded world, the leading trade show covering hardware, software, tools, and related services for the embedded systems market, took place in Nuremberg, Germany... Read more.
Andes Technology Demo of Its RISC-V IP in a Spherical Image Processor and Meta’s AI Accelerator
Marc Evans, Director of Business Development and Marketing at Andes Technology, demonstrates the company’s latest edge AI and vision technologies and products... Read more.
Design and implementation of a hardened cryptographic coprocessor for a RISC-V 128-bit core
Cryptography is a way of encoding and decoding information to guarantee its confidentiality and protection from unauthorised individuals. Within the realm of digital... Read more.
Security digital twin for RISC-V space chip
UK defence contractor BAE Systems is using a security digital twin of a RISC-V processor from SiFive for a radiation hardened chip for space applications. Cycuity... Read more.
Embracing Multicore and RISC-V Architectures in SoC Design
What you’ll learn: Discover the advantages of the open-source RISC-V architecture in promoting efficiency and innovation in semiconductor design. Learn how RISC-V... Read more.
Embedded World, Nuremberg: Tasking Strengthens its Ecosystem with LDRA Acquisition and RISC-V Support
At Embedded World in Nuremberg, Germany, Maurizio Di Paolo Emilio, Editor-in-Chief of Embedded.com, interviewed Gregor Zink, CEO, and Christoph Herzog, CTO of Tasking.... Read more.