TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor
By Wenbo Yin, Vice President of IC Design, TetraMem Inc. Introduction The rapid proliferation of artificial intelligence (AI) across a growing number of hardware... Read more.
TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor
By Wenbo Yin, Vice President of IC Design, TetraMem Inc. Introduction The rapid proliferation of artificial intelligence (AI) across a growing number of hardware... Read more.
Rivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoC
NX45 Becomes the Only RISC-V Core to Pass Rivos’ Rigorous Verification Process After Extensive Evaluation of Leading RISC-V Cores San Jose, CA – Sep. 11, 2024 —... Read more.
Rivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoC
NX45 Becomes the Only RISC-V Core to Pass Rivos’ Rigorous Verification Process After Extensive Evaluation of Leading RISC-V Cores San Jose, CA – Sep. 11, 2024—... Read more.
Andes Technology is Expanding RISC-V’s Horizons in High-Performance Computing Applications
By: Dr. Charlie Su, President and CTO, Andes Technology Corp. At Andes Technology, we are excited to share some of our latest advancements and insights into the... Read more.
[VIDEO] Accelerating RISC-V testbench development with open source RISC-V RTL and emulation
Today’s shorter product time to market makes silicon verification runway shorter. Tenstorrent is working on CPUs based on RISC-V architecture for many AI applications.... Read more.
[VIDEO] A Holistic Approach to RISC-V Processor Verification
Processors using the open standard RISC-V instruction set architecture (ISA) are becoming more and more common, with an estimated 30% of SoCs designed in 2023 containing... Read more.
[VIDEO] The Future of Compute
Patrick Little, SiFive Chairman, President and CEO talks about how RISC-V is shaping the future of compute, how SiFive is gaining momentum from applications from... Read more.
Codeplay Brings RISC-V Support to the oneAPI Construction Kit
RISC-V is the fast growing, open standard instruction set architecture (ISA) for processors of all types including CPUs and accelerators. These processors can be... Read more.
RISC-V is Built for Artificial Intelligence and SiFive Solutions for AI
RISC-V inventor and SiFive Founder Krste Asanovic discusses why RISC-V is “built for” AI applications and how SiFive is working from the edge to the... Read more.