Segger and Codasip Announce Cooperation on RISC-V
Monheim am Rhein & Munich, Germany – June 22nd, 2021 – SEGGER and Codasip announce that SEGGER’s J-Link debug probes and its Embedded Studio IDE fully... Read more.
SiFive aims to challenge Arm with new tech, pairs with Intel on effort | Stephen Nellis, Reuters
June 22 (Reuters) - SiFive Inc on Tuesday released a new computing chip design that aims to challenge Arm Ltd's dominance in smartphone chips and said it would pair... Read more.
Life in a Formal Verification Lane | Shinavi Shah, SemiWiki.com
This summer, I got the opportunity to work as a Formal Verification Intern with Axiomise for six weeks. I’m a keen designer and love working in design and architecture.... Read more.
Video: RISC-V vs x86 – History and Key Differences Explained
x86 or x86-64 is the name of the architecture used by Intel and AMD to make their processors. RISC-V is a relatively new architecture that, besides being RISC rather... Read more.
SiFive’s brand-new P550 is one of the world’s fastest RISC-V CPUs | Jim Salter, arsTechnica
Today's RISC-V microcontrollers may lead to future RISC-V phones and laptops.
Today, RISC-V CPU design company SiFive launched a new processor family with two core... Read more.
Argonne, ORNL Award Codeplay Contract to Strengthen SYCL Support for AMD GPUs | HPCwire
LEMONT, Ill., OAK RIDGE, Tenn., and EDINBURGH, England, June 17, 2021 — Argonne National Laboratory (Argonne) in collaboration with Oak Ridge National Laboratory... Read more.
SEGGER and Codasip Announce Cooperation on RISC-V
SEGGER and Codasip announce that SEGGER’s J-Link debug probes and its Embedded Studio IDE fully support Codasip’s RISC-V processors, right out-of-the-box.
SEGGER’s... Read more.
