DeepComputing and Xcalibyte announce the ROMA laptop will be powered by TH1520 – the first SoC from Wujian 600’s platform by Alibaba T-Head | Xcalibyte
Alibaba T-Head recently released a brand-new high-performance RISC-V SoC named the TH1520 at The RISC-V Summit China 2022. According to Alibaba “TH1520 demonstrates... Read more.
Dev board for 32bit GigaDevice RISC-V | Steve Bush, Electronics Weekly
MikroElektronika has launched a development board for GigaDevice’s GD32VF103VBT6 32bit RISC-V microcontroller in its SiBrain format. Mikroe is the company is behind... Read more.
Linux 6.0 release – Main changes, Arm, RISC-V, and MIPS architectures | Jean-Luc Aufranc, CNX Software
So, as is hopefully clear to everybody, the major version number change is more about me running out of fingers and toes than it is about any big fundamental changes....... Read more.
XuanTie Security System Promotes Rapid Migration of Security Applications from Arm to RISC-V | Vincent Cui, Alibaba Cloud
Recently at the RISC-V Summit China 2022 a new high-performance RISC-V-based chip platform named Wujian 600 and the TH1520 chip prototype was revealed. These products... Read more.
SiFive has licenses C++ library for Risc-V | Steve Bush, Electronics Weekly
IC intellectual property company SiFive has licensed Segger’s emRun++ C++ library for Risc-V, a library optimised for GCC/LLVM-based tool chains and embedded systems,... Read more.
Researchers Build a RISC-V Chip That Calculates in Posits, Boosting Accuracy for ML Workloads | Gareth Halfacree, Hackster.io
Designed as an alternative to floating-point numbers, posits may prove key to boosting machine learning performance. A team of scientists at the Complutense University... Read more.
Framework Based On An RISC-V Microprocessor Supporting LiM Operations | Coluccio, A.; Ieva, A.; Riente, F.; Roch, M.R.; Ottavi, M.; Vacca, M. RISC-Vlim, Semiconductor Engineering
A new technical paper titled “RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures” was published by researchers at Politecnico di Torino (Italy),... Read more.
Acceleration Robotics Partners with PlanV for a Robotics-Specific Open Source RISC-V Microcontroller | Gareth Halfacree, Hackster.io
Designed specifically for ROS 2, the roscore-v RISC-V microcontroller promises reduced latencies and new real-time capabilities. Performance-boosting specialist... Read more.
Google experiments with RISC-V | Nick Farrell, Fudzilla
SiFive RISC-V chips are being used by Google to run some of its AI workloads and tested in Google datacentres. SiFive’s Intelligence X280 is a multi-core... Read more.
The Automotive Space Gears Up to Take on RISC-V | Murray Slovick, Electronic Design
SiFive is creating a lineup of compute IP for MCUs, MPUs, and soon, SoCs, as well as vector-processing solutions tailored for automotive applications. The first... Read more.