Imperas announces the latest updates to RVVI and welcomes the adoption by many leading RISC V processor developers | Imperas Software
Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates for RVVI (RISC-V Verification Interface) for RISC-V processor... Read more.
Open Standard RISC-V Verification Interface (RVVI) for SOC testing | Nick Flaherty, EE News Europe
Imperas Software in the UK has extended the RVVI (RISC-V Verification Interface) with virtual peripherals to support asynchronous events and system level interrupts.
RVVI is... Read more.
China pins hopes on local RISC-V start-ups to crack Western monopoly on CPU chips | Che Pan, South China Morning Post
China is seeing a chance to improve its self sufficiency in microprocessors, the heart of every smart device, through the open-standard RISC-V chip design architecture,... Read more.
Progress in Porting Android onto RISC-V: Android 12 upgrade, vendor modules and TensorFlow Lite | Mao Han, Alibaba Cloud
Last year Alibaba T-Head reported that the basic features of Android had been ported onto RISC-V-based Xuantie cores. Since then more effort has been spent on Android... Read more.
ISA Extension For Low-Precision NN Training On RISC-V Cores | Luca Bertaccini, Gianna Paulin, Tim Fischer, Stefan Mach, Luca Benini, Semiconductor Engineering
Abstract
“Low-precision formats have recently driven major breakthroughs in neural network (NN) training and inference by reducing the memory footprint of the... Read more.
Europe steps up as RISC-V ships 10bn cores | Nick Flaherty, EE News Europe
It may come as a surprise that over 10 billion RISC-V processor cores have shipped. After all, it took ARM 17 years to reach that milestone in 2008, and RISC-V could... Read more.
RISC-V Opens the Door on 48-bit Computing | Agam Shah, HPC Wire
There’s a growing interest among silicon providers backing RISC-V to introduce 48-bit computing in custom chips to meet their specific requirements.
The 48-bit... Read more.
Imperas and Breker partner for Risc-V system-level verification | Steve Bush, Electronics Weekly
RISC-V simulation company Imperas Software has announced a partnership with Breker Verification Systems, a provider of test content synthesis for verification environments,... Read more.
First RISC-V-Based SoC FPGA Enters Mass Production | Microchip Technology, EE Time Asia
The first SoC field programmable gate array (FPGA) to support the royalty-free RISC-V open Instruction Set Architecture (ISA) has entered volume production, marking... Read more.
SiFive arrives in Cambridge to hire 100 for ascendant RISC-V computing | Mike Scialom, Cambridge Independent
SiFive, the California-based founder and leader of RISC-V computing, has opened its new UK Research & Development (R&D) Centre at WeWork on Station Road... Read more.