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Exploring the Benefits of RISC-V ISA for Posit Arithmetic at HiPEAC Conference | Federico – The AI Blog
News Espressif Reveals ESP32-P4: A High-Performance MCU with Numerous IO-Connectivity and Security Features | Espressif Systems
Ventana Introduces CES Audience to World’s Highest Performance RISC-V CPU, Veyron V1 | Ventana Micro SystemsA Bottom-Up Methodology for the Fast Assessment of CNN Mappings on Energy-Efficient Accelerators | Guillaume Devic, Gilles Sassatelli and Abdoulaye Gamatié
Run 32-bit applications on 64-bit Linux kernel | LIU Zhiwei, GUO Ren| T-Head Division of Alibaba Cloud
Ventana Introduces CES Audience to World’s Highest Performance RISC-V CPU, Veyron V1 | Ventana Micro Systems, Yahoo! Finance
RISC-V could become a first-class citizen for Android, Pixel 7a hands-on video leaked, and GeForce Now adds a RTX 4080 tier | Brad Linder, Liliputing
SpacemiT Makes Important Breakthroughs in RISC-V High-Performance Cores | SpacemiT
Breker Verification Systems Unveils Easy-To-Adopt Integrity FASTApps Targeting RISC-V Processor Core, SoC Verification Scenarios | Breker Verification Systems
Google wants RISC-V to be a “tier-1” Android architecture | Ron Amadeo, Ars Technica
RISC-V Summit 2022: All Your CPUs Belong to Us | Kevin Krewell, EE Times
Mouser Now Stocking Renesas Electronics RZ/Five-RISC-V Microprocessor for IoT Endpoint and Industrial Gateway Apps | ELE Times
Breker Verification Systems Joins RISC-V International as a Strategic Member to Drive Cache Coherency and SoC Integration Verification Methodologies | Breker Verification Systems
RISC-V Takes Embedded World 2022 by Storm | Max Maxfield, Electronic Engineering Journal
German startup MachineWare announces a RISC-V simulator | Scientific Computing World
Esperanto is leading the RISC-V revolution for AI and enabling a new level of AI performance | Esperanto.ai
MachineWare RISC-V simulator for software developers | Brittany Hainzinger, App Developer Magazine
RISC-V International Adds Four ISA Chip Specification Approvals | Todd R Weiss, Futurum Research
Build Open Silicon with Google | Google Open Source BlogEnabling Heterogeneous, Multicore SoC Research with RISC-V and ESP | Joseph Zuckerman, Paolo Mantovani, Davide Giri, Luca P. Carloni
SiFive opens Cambridge RISC-V design centre | Nick Flaherty, EE News Europe
Pine64 Teases RISC-V Based Raspberry Pi Alternative | Ian Evenden, Tom’s HardwareNew startup MachineWare enables ultra-fast RISC-V simulation | Electronic Engineering Journal
OpenHW Group announces RISC-V CORE-V MCU kit | Robin Mitchell, Electropages
Exploring the Benefits of RISC-V ISA for Posit Arithmetic at HiPEAC Conference | Federico – The AI BlogI am excited to announce that I will be giving a talk at the HiPEAC conference on the RISC-V ISA for posit arithmetic! HiPEAC is…
News Espressif Reveals ESP32-P4: A High-Performance MCU with Numerous IO-Connectivity and Security Features | Espressif SystemsEspressif Systems (SSE: 688018.SH) today announces the upcoming release of its latest SoC, ESP32-P4. It is powered by a dual-core RISC-V CPU with an AI…
Ventana Introduces CES Audience to World’s Highest Performance RISC-V CPU, Veyron V1 | Ventana Micro SystemsVentana Micro Systems announced that it will be presenting at the Consumer Electronics Show being held in Las Vegas (CES) between Jan. 5-8 the Veyron V1, the first RISC-V…
A Bottom-Up Methodology for the Fast Assessment of CNN Mappings on Energy-Efficient Accelerators | Guillaume Devic, Gilles Sassatelli and Abdoulaye GamatiéAbstract - The execution of machine learning (ML) algorithms on resource-constrained embedded systems is very challenging in edge computing. To address this issue, ML accelerators…
Run 32-bit applications on 64-bit Linux kernel | LIU Zhiwei, GUO Ren| T-Head Division of Alibaba Cloud1. Introduction Many architectures support run 32-bit applications on 64-bit processors. On x86, in order to achieve running 16-bit or 32-bit applications in long mode,…
Ventana Introduces CES Audience to World’s Highest Performance RISC-V CPU, Veyron V1 | Ventana Micro Systems, Yahoo! FinanceVentana Micro Systems Inc. announced today that it will be presenting at the Consumer Electronics Show being held in Las Vegas (CES) between Jan. 5-8 the Veyron V1, the first…
RISC-V could become a first-class citizen for Android, Pixel 7a hands-on video leaked, and GeForce Now adds a RTX 4080 tier | Brad Linder, LiliputingRISC-V is an open, royalty-free chip architecture positioned as an alternative to the ARM and x86 chips that dominate the PC, mobile, server, and embedded…
SpacemiT Makes Important Breakthroughs in RISC-V High-Performance Cores | SpacemiTWe’re excited to share some recent progress in the development of our first-generation RISC-V fusion computing processor core - the X100. X100 has already made…
Breker Verification Systems Unveils Easy-To-Adopt Integrity FASTApps Targeting RISC-V Processor Core, SoC Verification Scenarios | Breker Verification SystemsAutomated Test Generation Verification IP Elements Focus on Difficult Scenarios for Broad Range of Processor Cores and SoCs. Breker Verification Systems, the leading provider of…
Google wants RISC-V to be a “tier-1” Android architecture | Ron Amadeo, Ars TechnicaGoogle's keynote at the RISC-V Summit promises official, polished support. Over the holiday break, the footage from the recent "RISC-V Summit" was posted for the world to…
RISC-V Summit 2022: All Your CPUs Belong to Us | Kevin Krewell, EE TimesIn a recent guest editorial here on EE Times, legendary professor David Patterson wrote about busting the five myths around the RISC-V instruction set architecture (ISA). At…
Mouser Now Stocking Renesas Electronics RZ/Five-RISC-V Microprocessor for IoT Endpoint and Industrial Gateway Apps | ELE TimesMouser Electronics, the industry’s leading New Product Introduction (NPI) distributor with the widest selection of semiconductors and electronic components, is now stocking the RZ/Five-RISC-V microprocessor…
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Breker Verification Systems Joins RISC-V International as a Strategic Member to Drive Cache Coherency and SoC Integration Verification Methodologies | Breker Verification SystemsBreker Verification Systems, the leading provider of advanced test content synthesis solutions, including RISC-V Cache Coherency and other SoC integration Verification Intellectual Property (VIP) in…
RISC-V Takes Embedded World 2022 by Storm | Max Maxfield, Electronic Engineering JournalI love computers (but only in a manly-man way, you understand). I’m not talking about the end-products that sit on our desks, hang out in…
German startup MachineWare announces a RISC-V simulator | Scientific Computing WorldMachineWare aims to disrupt semiconductor design with the introduction of its high-speed functional simulator, SIM-V. Headquartered in Aachen and emerging from stealth mode in May,…
Esperanto is leading the RISC-V revolution for AI and enabling a new level of AI performance | Esperanto.aiThe ET-SoC-1 inference chip is designed to be the world’s highest performance RISC-V commercial chip, delivering a massively parallel, flexible architecture that combines exceptional performance…
MachineWare RISC-V simulator for software developers | Brittany Hainzinger, App Developer MagazineMachineWare is set to revolutionize semiconductor design with its high-speed functional RISC-V simulator, SIM-V. SIM-V, the company’s flagship product, combines unprecedented simulation performance with exceptional…
RISC-V International Adds Four ISA Chip Specification Approvals | Todd R Weiss, Futurum ResearchRISC-V International Adds Four ISA Chip Specification Approvals Analyst Take: RISC-V International’s latest expansion of its RISC-V ISA specifications and extensions for chip makers is…
Build Open Silicon with Google | Google Open Source BlogTLDR; the Google Hardware Toolchains team is launching a new developer portal, developers.google.com/silicon, to help the developer community get started with its Open MPW shuttle…
Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP | Joseph Zuckerman, Paolo Mantovani, Davide Giri, Luca P. CarloniHeterogeneous, multicore SoC architectures are a critical component of today's computing landscape. However, supporting both increasing heterogeneity and multicore execution are significant design challenges. Meanwhile,…
SiFive opens Cambridge RISC-V design centre | Nick Flaherty, EE News EuropeRISC-V chip designer SiFive has opened its new UK Research & Development (R&D) Centre headquartered in Cambridge. SiFive plans to hire over 100 employees across…
Pine64 Teases RISC-V Based Raspberry Pi Alternative | Ian Evenden, Tom’s HardwarePine64, maker of many fine SBCs including the Rock64 and Quartz64 (opens in new tab), is preparing to dip its toe into the choppy waters…
New startup MachineWare enables ultra-fast RISC-V simulation | Electronic Engineering JournalHeadquartered in Aachen and emerging from stealth mode in May, MachineWare is set to revolutionize semiconductor design with its high-speed functional RISC-V simulator, SIM-V. SIM-V, the company’s…
OpenHW Group announces RISC-V CORE-V MCU kit | Robin Mitchell, ElectropagesRecently at Embedded World 2022, OpenHW demonstrated their latest RISC-V development board that shows off their CORE-V MCU. What advantages will RISC-V present to the…