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T-Head XuanTie C908 RISC-V core targets AIoT applications | Jean-Luc Aufranc, CNX Software
DongshanPI-D1s is a RISC-V Development Board for Less Than $20 | Ian Evenden, Tom’s HardwareDongshanPI-D1s – An Allwinner D1s RISC-V development board designed to teach programming | Jean-Luc Aufranc, CNX Software
SiFive releases high-performance processors for small-size, high-volume applications | Judy Lin, DIGITIMES Asia
High-performance RISC-V cores from SiFive | Steve Bush, Electronics Weekly
The Android Open Source Project Is Now RISC-V Compatible | Laveesh Kocher, Open Source For You
SiFive aims for ARM with high performance RISC-V vector cores | Nick Flaherty, EE News Europe
Ubuntu continues expanding RISC-V support – now, the $17 Sipeed LicheeRV | Tobias Mann, The Register
5 Good Things About RISC-V | Filip Benna, Semiconductor Engineering
WCH Launches a Sub-10¢ RISC-V Microcontroller, While a $6.90 Dev Board Gets You Started | Gareth Halfacree, Hackster.iouConsole is a modular Arm for RISC-V handheld computer with optional 4G connectivity | Jean-Luc Aufranc
Ubuntu 22.10 Up And Running On The LicheeRV ~$19 RISC-V Board | Michael Larabel, Phoronix
Codasip University Program spurs innovation and boosts curriculums | Codasip
SEGGER collaborates with HPMicro making Embedded Studio for RISC-V available at no cost | SEGGER32bit RISC-V cores are customisable for TensorFlowLite AI | Nick Flaherty, EE News Europe
Renesas expands options with Andes-based RISC-V MPU | Nitin Dahad, Embedded.com
MPU leverages 64-bit RISC-V core | Susan Nordyk, EDN$39 MangoPi-Nezha MQ RISC-V developer board runs OpenWrt, Debian, or RT-Smart RTOS (Crowdfunding) | Jean-Luc Aufranc, CNX Software
Open standard for RISC-V verification is announced at DVCon | Caroline Hayes, Electronics Weekly
Imperas announces RISC-V Physical Memory Protection (PMP) Architectural Validation test suite for high quality security applications | ImperasM5Stamp C3U IoT module relies on ESP32-C3’s own USB interface for firmware programming | Jean-Luc Aufranc, CNX Software
Imperas announces RISC-V PMP Architectural Validation test suite | Neil Tyler, New Electronics
Imperas announces RISC-V Physical Memory Protection (PMP) Architectural Validation test suite for high quality security applications | Electronic Engineering JournalRISC-V design challenge – Get a free board, RISC-V chips, and cash prizes | Jean-Luc Aufranc, CNX Software
T-Head XuanTie C908 RISC-V core targets AIoT applications | Jean-Luc Aufranc, CNX SoftwareWe’ve seen two announcements of high-end RISC-V cores this week with the SiFive P670 and Andes AX65 processors each with a 4-way out-of-order pipeline, but Alibaba’s T-Head Semiconductor Xuantie…
DongshanPI-D1s is a RISC-V Development Board for Less Than $20 | Ian Evenden, Tom’s HardwareAnother RISC-V development system has become available — this time with an Allwinner D1s processor on board in a package designed to teach programming. The DongshanPI-D1s, brought…
DongshanPI-D1s – An Allwinner D1s RISC-V development board designed to teach programming | Jean-Luc Aufranc, CNX SoftwareThe DongshanPI-D1s development board is comprised of a soldered-on Allwinner D1s RISC-V system-on-module board (SoM) and a carrier board with two 40-pin headers and a…
SiFive releases high-performance processors for small-size, high-volume applications | Judy Lin, DIGITIMES AsiaRISC-V computing startup SiFive, Inc., announced two new products that address the need for high performance and efficiency in small-size, high-volume applications like wearables, smart-home…
High-performance RISC-V cores from SiFive | Steve Bush, Electronics Weekly“P670 and P470 are specifically designed for the most demanding workloads for wearables and other advanced consumer applications,” said SiFive v-p Chris Jones. “We have…
The Android Open Source Project Is Now RISC-V Compatible | Laveesh Kocher, Open Source For YouA crucial advancement for the technology is the porting of the Android Open Source Project (AOSP) to the RISC-V processor architecture. The AOSP has begun…
SiFive aims for ARM with high performance RISC-V vector cores | Nick Flaherty, EE News EuropeSiFIve has developed two families of RISC-V cores with vector processing for high volume applications such as wearables, smart home, industrial automation, AR/VR, and other…
Ubuntu continues expanding RISC-V support – now, the $17 Sipeed LicheeRV | Tobias Mann, The RegisterAs progress revealed on Android port to the open ISA. Canonical has brought its Ubuntu Linux operating system to another RISC-V system: this week, Sipeed's…
5 Good Things About RISC-V | Filip Benna, Semiconductor EngineeringA burgeoning ecosystem is driving a virtuous spiral of choice and innovation. RISC-V has been around for some time now, and if you are here…
WCH Launches a Sub-10¢ RISC-V Microcontroller, While a $6.90 Dev Board Gets You Started | Gareth Halfacree, Hackster.ioDesigned for less-computationally-demanding workloads, this 32-bit RISC-V chip is priced extremely aggressively. WCH Electronics has launched a new, low-cost RISC-V microcontroller chip running at up…
uConsole is a modular Arm for RISC-V handheld computer with optional 4G connectivity | Jean-Luc AufrancClockwork’s uConsole is a modular handheld computer with a 5-inch display, a built-in keyboard, and based on a carrier board supporting various Arm or RISC-V…
Ubuntu 22.10 Up And Running On The LicheeRV ~$19 RISC-V Board | Michael Larabel, PhoronixIn addition to supporting the SiFive HiFive Unmatched, Allwinner D1 Nezha, and VisionFive RISC-V board support, Canonical has formally announced Ubuntu 22.10 for the LicheeRV as a $16~19+…
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Codasip University Program spurs innovation and boosts curriculums | CodasipKeith Graham appointed Head of University Program. Codasip, the leader in processor design automation, has launched a University Program to help the next generation of…
SEGGER collaborates with HPMicro making Embedded Studio for RISC-V available at no cost | SEGGERSEGGER today announces its partnership with HPMicro Semiconductor Inc. (HPMicro), a leading supplier of high-performance MCUs and embedded solutions. The partnership focuses on making SEGGER’s…
32bit RISC-V cores are customisable for TensorFlowLite AI | Nick Flaherty, EE News EuropeCodasip has launched two 32bit RISC-V processor cores that can be optimised for machine learning applications. The L31 and L11 are the latest cores optimized…
Renesas expands options with Andes-based RISC-V MPU | Nitin Dahad, Embedded.comRenesas Electronics Corporation said it has expanded the options for developers using its general-purpose microprocessor units (MPUs), with a new MPU built around a 64-bit…
MPU leverages 64-bit RISC-V core | Susan Nordyk, EDNRenesas offers the RZ/Five general-purpose MPU, its first built around a 64-bit RISC-V core from Andes Technology. The RZ/Five is optimized to provide the performance…
$39 MangoPi-Nezha MQ RISC-V developer board runs OpenWrt, Debian, or RT-Smart RTOS (Crowdfunding) | Jean-Luc Aufranc, CNX SoftwareMangoPi-Nezha MQ tiny developer board with Allwinner F133-A (aka Allwinner D1s) RISC-V processor with 64MB on-chip RAM has just launched on Crowd Supply for $39, and delivery is…
Open standard for RISC-V verification is announced at DVCon | Caroline Hayes, Electronics WeeklyAt this year’s (virtual) functional design and verification conference, DVCon US 2022, the RISC-V Verification Interface (RVVI) was announced by Imperas Software. The interface is available at github.…
Imperas announces RISC-V Physical Memory Protection (PMP) Architectural Validation test suite for high quality security applications | ImperasThe latest ImperasDV test suite for PMP covers the full envelope of configuration options. Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the…
M5Stamp C3U IoT module relies on ESP32-C3’s own USB interface for firmware programming | Jean-Luc Aufranc, CNX SoftwareM5Stamp C3U is an update of the M5Stamp C3 RISC-V IoT module with heat-resistant cover, support for WiFi 4 and Bluetooth 5.0, that does without CH9102 USB…
Imperas announces RISC-V PMP Architectural Validation test suite | Neil Tyler, New ElectronicsThe open standard ISA (Instruction Set Architecture) of RISC-V offers developers a wide range of standard extensions and options that support the design of an…
Imperas announces RISC-V Physical Memory Protection (PMP) Architectural Validation test suite for high quality security applications | Electronic Engineering JournalThe latest ImperasDV test suite for PMP covers the full envelope of configuration options. Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced…
RISC-V design challenge – Get a free board, RISC-V chips, and cash prizes | Jean-Luc Aufranc, CNX SoftwareA little while ago, I wrote about WCH CH32V307 32-bit RISC-V MCU that was found in a board with eight UART ports that could be controlled over…