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Porting GNOME OS to Microchip’s PolarFire® SoC FPGA Icicle Kit for the First Time | Microchip

Customers often require support to bring up new boards and architectures on Linux. Our Mi-V ecosystem partner, Codethink’s specialty is board bring-up and they perform…

Andes Technology RISC-V Processors Reveal Outstanding Performance and Efficiency in MLPerf Tiny | Andes Technology

Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International,…

DAC 2022 – Is it too risky not to adopt RISC-V? | Brett Cline, Codasip

I was fortunate enough to attend the 59th Design Automation Conference (DAC) in San Francisco last week. Aside from the Covid closure in 2020 I’ve…

Co-developing Machine Learning with a RISC-V vector core using Renode for Google Research | Antmicro

The landscape of Machine Learning software libraries and models is evolving rapidly, and to satisfy the ever-increasing demand for memory and compute while managing latency,…

Accelerating ML Recommendation With Over 1,000 RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip | David R. Ditzel, Esperanto Technologies Inc

Machine learning (ML) recommendation workloads have demanding performance and memory requirements and, to date, have largely been run on servers with x86 processors. To accelerate…

RISC-V Standardizes E-Trace and Binary Interface | William G. Wong, Electronic Design

RISC-V International has released a number of new specifications that enhance the RISC-V ecosystems. I talked with Chief Technology Officer for RISC-V International, Mark Himelstein, about…

Updated: Imagination’s first real-time embedded RISC-V CPU | Steve Bush, Electronics Weekly

Imagination Technologies has announced its first real-time embedded RISC-V CPU. Called IMG RTXM-2200, the 32bit core is aimed at SoCs for networking, packet management, storage…

Codasip opens RISC-V design centre in Greece | Nick Flaherty, EE News Europe

Codasip has opened a new RISC-V design facility in Greece, hiring Giorgos Nikiforos from Apple as director. Nikiforos brings decades of engineering experience in hardware…

YD-CH32V307VCT6 RISC-V MCU board comes with Ethernet and plenty of I/Os | Jean-Luc Aufranc, CNX Software

  At the beginning of the year, we wrote about WCH CH32V307 RISC-V microcontroller and a development board with 8 UART ports controlled over Ethernet.…

RISC-V Guns for Raspberry Pi, Legacy Chips | Lucas Laursen, IEEE Spectrum

Two hardware makers are planning to offer chips later this year featuring the RISC-V free and open architecture standard, joining the US $180 Linux-capable StarFive…

RISC-V Serves Up Open-Source Possibilities for the Future | Cabe Atwell, Electronic Design

This article is part of the TechXchange: RISC-V: The Instruction-Set Alternative What you’ll learn: What is RISC-V? The basics of RISC-V. Applications and uses of…

Joint venture unveils world’s first RISC-V laptop | Robin Mitchell, Electropages

As RISC-V continues to push the boundaries of open-source computing, a joint venture between DeepComputing and Xcalibyte has developed the world’s first RISC-V laptop set…

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KVM Changes Land In Linux 5.16: RISC-V Hypervisor Support, AMD PSF Control Bit | Michael Larabel, Phoronix

Last week the Kernel-based Virtual Machine (KVM) feature patches were sent out and subsequently merged for Linux 5.16. Arguably most notable for KVM with Linux…

How the RISC-V Atomic Extension Gives You Superior Bit Manipulation Capabilities | Bill Giovino, Digi-Key

The rate of RISC-V architecture adoption is quickly snowballing, and for good reason, its influence in the industry is increasing. Besides the core architecture and…

Codasip Appoints Brett Cline to Drive Company Growth Worldwide | Codasip

Codasip, the leading supplier of customizable RISC-V processor IP, today announced the company has made a senior appointment to boost its global sales effort, with…

What Computing Tech Will Drive Future Space Exploration? | Michelle Hampson, IEEE Spectrum

At the heart of every successful space mission is a sophisticated and capable computer system. In the 1960s, relatively basic computing systems took humankind to…

SME: Scalable Masking Extensions | Ben Marshall and Dan Page, University of Bristol and PQShield Ltd

Abstract: Supporting masking countermeasures for non-invasive side-channel security in instructions set architectures is a hard problem. Masked operations often have a large number of inputs…

Looking Towards the Future: FreeBSD on the RISC-V Architecture | Klara

The majority of people in the tech community are well aware of the two main chip architectures: x86 and ARM. Each has its own strengths…

Pixel 6: Setting a new standard for mobile security | Dave Kleidermacher, Jesse Seed, Brandon Barbello, and Stephan Somogyi, Android, Pixel & Tensor security teams, Google Security Blog

With Pixel 6 and Pixel 6 Pro, we’re launching our most secure Pixel phone yet, with 5 years of security updates and the most layers…

RISC-V-Based VEGA Brings Continual Learning to TinyML with an Order of Magnitude Efficiency Gain | Gareth Halfacree, Hackster.io

A team of computer scientists have developed a RISC-V-based platform for embedded machine learning workloads — and say it offers 65 times the performance and…

High-Level Synthesis For RISC-V | Brian Bailey, Semiconductor Engineering

Abstraction is the key to custom processor design and verification, but defining the right language and tool flow is a work in progress. High-quality RISC-V…

Kneron Edge AI SoC Powered by Andes RISC-V Processor Core D25F | Andes Technology

Kneron Inc., the San Diego-based Edge AI solution provider, together with Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance,…

Truechip Introduces Silicon IP for Network on Chip (NOC) Focused for TileLink RISC-V Chips | Truechip

Truechip, the Verification IP Specialist, today announced that it has introduced a Silicon IP to its product offering in addition to its existing Verification IP…