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SEGGER collaborates with HPMicro making Embedded Studio for RISC-V available at no cost | SEGGER
32bit RISC-V cores are customisable for TensorFlowLite AI | Nick Flaherty, EE News Europe
Renesas expands options with Andes-based RISC-V MPU | Nitin Dahad, Embedded.com
MPU leverages 64-bit RISC-V core | Susan Nordyk, EDN
$39 MangoPi-Nezha MQ RISC-V developer board runs OpenWrt, Debian, or RT-Smart RTOS (Crowdfunding) | Jean-Luc Aufranc, CNX Software
Open standard for RISC-V verification is announced at DVCon | Caroline Hayes, Electronics Weekly
Imperas announces RISC-V Physical Memory Protection (PMP) Architectural Validation test suite for high quality security applications | ImperasM5Stamp C3U IoT module relies on ESP32-C3’s own USB interface for firmware programming | Jean-Luc Aufranc, CNX Software
Imperas announces RISC-V PMP Architectural Validation test suite | Neil Tyler, New Electronics
Imperas announces RISC-V Physical Memory Protection (PMP) Architectural Validation test suite for high quality security applications | Electronic Engineering JournalRISC-V design challenge – Get a free board, RISC-V chips, and cash prizes | Jean-Luc Aufranc, CNX Software
Linux 5.18 To Bring RISC-V sv57 Support For 5-Level Page Tables | Michael Larabel, Phoronix
Haawking licenses SEGGER’s emRun for RISC-V | SEGGER
Hot Chips Concludes An Amazing Lineup of AI Chip Companies | Karl Freund, Forbes
Apple Exploring RISC-V, Hiring RISC-V ‘High Performance’ Programmers | Anton Shilov, Tom’s Hardware
Rivos Inc: A Chip Off The Old Block? New RISC-V Startup Garners Many Senior CPU Architects From Apple, Google, Marvell, Qualcomm, Intel, and AMD | Dylan Patel, Semi Analysis
Ventana Micro Systems raises $38M to design datacenter RISC-V processors | Dean Takahashi, Venture Beat
efabless, Google and SkyWater Are Enabling Us Mere Mortal Makers to Design Our Own Open Source ASICs | Tom Fleet, Hackster.io
AB32VG1 – An Arduino Uno-like RISC-V based development Board Designed for Audio Applications | Electronics-Lab
Linux 5.14 Release – Main changes, Arm, MIPS, and RISC-V architectures | Jean-Luc Aufranc, CNX Software
Accelerating exhaustive and complete verification of RISC-V processors | Ashish Darbari, Axiomise
Podcast: David Patterson – “RISC-V, Tesla’s D1 Chip, The Future of Hardware For Machine Learning” | Marwa ElDiwiny, Soft Robotics Podcast
Andes Technology and Cyberon Collaborate to Provide Edge-Computing Voice Recognition Solution on DSP-capable RISC-V Processors | Chip EstimateImagination Technologies to design RISC-V cores | Jean-Luc Aufranc, CNX Software
SEGGER collaborates with HPMicro making Embedded Studio for RISC-V available at no cost | SEGGERSEGGER today announces its partnership with HPMicro Semiconductor Inc. (HPMicro), a leading supplier of high-performance MCUs and embedded solutions. The partnership focuses on making SEGGER’s…
32bit RISC-V cores are customisable for TensorFlowLite AI | Nick Flaherty, EE News EuropeCodasip has launched two 32bit RISC-V processor cores that can be optimised for machine learning applications. The L31 and L11 are the latest cores optimized…
Renesas expands options with Andes-based RISC-V MPU | Nitin Dahad, Embedded.comRenesas Electronics Corporation said it has expanded the options for developers using its general-purpose microprocessor units (MPUs), with a new MPU built around a 64-bit…
MPU leverages 64-bit RISC-V core | Susan Nordyk, EDNRenesas offers the RZ/Five general-purpose MPU, its first built around a 64-bit RISC-V core from Andes Technology. The RZ/Five is optimized to provide the performance…
$39 MangoPi-Nezha MQ RISC-V developer board runs OpenWrt, Debian, or RT-Smart RTOS (Crowdfunding) | Jean-Luc Aufranc, CNX SoftwareMangoPi-Nezha MQ tiny developer board with Allwinner F133-A (aka Allwinner D1s) RISC-V processor with 64MB on-chip RAM has just launched on Crowd Supply for $39, and delivery is…
Open standard for RISC-V verification is announced at DVCon | Caroline Hayes, Electronics WeeklyAt this year’s (virtual) functional design and verification conference, DVCon US 2022, the RISC-V Verification Interface (RVVI) was announced by Imperas Software. The interface is available at github.…
Imperas announces RISC-V Physical Memory Protection (PMP) Architectural Validation test suite for high quality security applications | ImperasThe latest ImperasDV test suite for PMP covers the full envelope of configuration options. Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the…
M5Stamp C3U IoT module relies on ESP32-C3’s own USB interface for firmware programming | Jean-Luc Aufranc, CNX SoftwareM5Stamp C3U is an update of the M5Stamp C3 RISC-V IoT module with heat-resistant cover, support for WiFi 4 and Bluetooth 5.0, that does without CH9102 USB…
Imperas announces RISC-V PMP Architectural Validation test suite | Neil Tyler, New ElectronicsThe open standard ISA (Instruction Set Architecture) of RISC-V offers developers a wide range of standard extensions and options that support the design of an…
Imperas announces RISC-V Physical Memory Protection (PMP) Architectural Validation test suite for high quality security applications | Electronic Engineering JournalThe latest ImperasDV test suite for PMP covers the full envelope of configuration options. Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced…
RISC-V design challenge – Get a free board, RISC-V chips, and cash prizes | Jean-Luc Aufranc, CNX SoftwareA little while ago, I wrote about WCH CH32V307 32-bit RISC-V MCU that was found in a board with eight UART ports that could be controlled over…
Linux 5.18 To Bring RISC-V sv57 Support For 5-Level Page Tables | Michael Larabel, PhoronixIt was just with Linux 5.17 that its RISC-V code adds "sv48" support for being able to handle more system memory by offering 48-bit virtual address space…
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Haawking licenses SEGGER’s emRun for RISC-V | SEGGERSEGGER Microcontroller announces that Beijing Haawking Technology, a specialist provider of RISC-V-based DSPs, has licensed SEGGER's emRun for RISC-V Runtime Library for distribution with its…
Hot Chips Concludes An Amazing Lineup of AI Chip Companies | Karl Freund, ForbesEvery year, I promise not to attend this tech-heavy confab of fast chips. And every year, I break that promise. Just too much to ignore!…
Apple Exploring RISC-V, Hiring RISC-V ‘High Performance’ Programmers | Anton Shilov, Tom’s HardwareApple is in the process of switching its PCs to Arm-based SoCs, but the company might not be putting all its eggs into one basket,…
Rivos Inc: A Chip Off The Old Block? New RISC-V Startup Garners Many Senior CPU Architects From Apple, Google, Marvell, Qualcomm, Intel, and AMD | Dylan Patel, Semi AnalysisWe recently wrote about a new CPU startup that has been garnering very impressive leadership and architects from all over. We have now confirmed the…
Ventana Micro Systems raises $38M to design datacenter RISC-V processors | Dean Takahashi, Venture BeatVentana Micro Systems has raised $38 million to design datacenter RISC-V processors as part of a push to create open hardware. Ventana’s chips will be…
efabless, Google and SkyWater Are Enabling Us Mere Mortal Makers to Design Our Own Open Source ASICs | Tom Fleet, Hackster.ioWe've witnessed a lot happening to help the plight of modern makers in recent years. We now have professionally-produced panels of PCBs, for mere peanuts.…
AB32VG1 – An Arduino Uno-like RISC-V based development Board Designed for Audio Applications | Electronics-LabBluetrum, a Chinese chip manufacturer known for its high-performance Bluetooth speakers and headsets, has designed an audio player microcontroller for audio applications and other general…
Linux 5.14 Release – Main changes, Arm, MIPS, and RISC-V architectures | Jean-Luc Aufranc, CNX SoftwareLinus Torvalds has just announced Linux 5.14 release which happens to almost coincide with the anniversary of the initial announcement of the “small” project on…
Accelerating exhaustive and complete verification of RISC-V processors | Ashish Darbari, AxiomiseAs processor architecture and design development becomes completely liberated with open-source RISC-V instruction set architecture (ISA), the race to get RISC-V silicon in our hands…
Podcast: David Patterson – “RISC-V, Tesla’s D1 Chip, The Future of Hardware For Machine Learning” | Marwa ElDiwiny, Soft Robotics PodcastListen to the full episode of Soft Robotics Podcast.
Andes Technology and Cyberon Collaborate to Provide Edge-Computing Voice Recognition Solution on DSP-capable RISC-V Processors | Chip EstimateCyberon Corporation, a leading embedded speech solution provider, and Andes Technology (TWSE: 6533), a major supplier for high efficiency, low-power 32/64-bit RISC-V processor cores, announced…
Imagination Technologies to design RISC-V cores | Jean-Luc Aufranc, CNX SoftwareNow better known for its PowerVR embedded GPUs, Imagination Technologies tried to enter the CPU market by purchasing MIPS Technologies and introducing microAptiv, interAptiv, and…