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RISC-V RV32I S-Type | Maven Silicon
Successful Conclusion of European Processor Initiative Phase One | European Processor Initiative
The Research of RISC-V for Embedded MCUs | RT-Thread
Linux 5.17 Adds Support For “The First Usable, Low-Cost RISC-V Platform” | Michael Larabel, Phoronix
HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing | Andreas Kurth, Björn Forsberg and Luca BeniniGentoo Linux Packages Up AMD ROCm, Makes Progress On RISC-V, LTO+PGO Python | Michael Larabel, Phoronix
The Chip Shortage, Giant Chips, and the Future of Moore’s Law | Samuel K. Moore, IEEE Spectrum
CH32V307 Chitu Development Board Tutorial: Use CMake to Develop | Yu Fan, VeriMake.io
MiG-V – Made in Germany RISC-V | HENSOLDT
Forces For Change And Competitive Intensity In Semiconductors | Michael Gurau, Forbes
21st Century Cryptography – Asynchronous ASIC | Jason Graalum, Galois
René Rebe Patches the Linux Kernel for “World’s First” Look at a Radeon RX 6700XT on a RISC-V PC | Gareth Halfacree, Hackster.io
WARP-V: A RISC-V CPU Core Generator Supporting MIPS ISA | Abhishek Jadhav, CNX Software
Previewing the Beagle V | Mender.io
Imperas updates Free reference model riscvOVPsimPlus with new RISC-V P (SIMD/DSP) extension and Architectural Validation Test Suites
Case Study: SiFive Launches Unmatched Board Remotely | Blue Clover Devices
RISC-V processor core for functional safety supported by development tools | electropages
Russia’s Elbrus has a RISC-V competitor as Yadro prepares native chips for launch | Gareth Halfacree, The RegisterCompsci eggheads bring OpenCL framework to RISC-V to push parallel performance | Gareth Halfacree, The Register
What is RISC-V? | Abhishek JadhavVideo: Decade of RISC-V Desktop?! HiFive Unmatched First Look
NSITEXE achieves world’s first RISC-V processor with vector extension certified for ISO 26262 ASIL D ready product |
Chinese Wearable Technology Firm Huami to Launch New OS with Better Understanding of Users | Pandaily
RISC-V RV32I S-Type | Maven SiliconThis video explains the RV32I S-Type instructions. RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats,…
Successful Conclusion of European Processor Initiative Phase One | European Processor InitiativeThe European Processor Initiative (EPI) has successfully completed its first three-year phase, delivering cutting-edge technologies for European sovereignty on time and within a limited budget,…
The Research of RISC-V for Embedded MCUs | RT-ThreadGreat RISC-V MCUs Display! Patrick Yang, CTO of WCH MicroElectronics has brought their Research of RISC-V for Embedded MCUs at the 2021 RT-Thread Global Tech…
Linux 5.17 Adds Support For “The First Usable, Low-Cost RISC-V Platform” | Michael Larabel, PhoronixIn addition to the prompt support for Qualcomm's Snapdragon 8 Gen 1, another exciting milestone for the in-development Linux 5.17 kernel is introducing mainline support for the…
HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing | Andreas Kurth, Björn Forsberg and Luca BeniniAbstract: Heterogeneous computers integrate general-purpose host processors with domain-specific accelerators to combine versatility with efficiency and high performance. To realize the full potential of heterogeneous…
Gentoo Linux Packages Up AMD ROCm, Makes Progress On RISC-V, LTO+PGO Python | Michael Larabel, PhoronixGentoo Linux developers were very busy over the course of 2021 for this popular rolling-release operating system choice. The Gentoo project has published their 2021…
The Chip Shortage, Giant Chips, and the Future of Moore’s Law | Samuel K. Moore, IEEE SpectrumWith COVID-19 shaking the global supply chain like an angry toddler with a box of jelly beans, the average person had to take a crash…
CH32V307 Chitu Development Board Tutorial: Use CMake to Develop | Yu Fan, VeriMake.ioCH32V307 Chitu Development Board Tutorial: Use CMake to Develop Try the tutorial.
MiG-V – Made in Germany RISC-V | HENSOLDTThe HENSOLDT Cyber MiG-V is a general purpose, logic-encrypted processor, Made in Germany, targeting high-security applications. Logic encryption hinders the insertion of hardware Trojans, giving…
Forces For Change And Competitive Intensity In Semiconductors | Michael Gurau, ForbesImportant financial and market forces are creating unprecedented growth and dynamism in the semiconductor industry. The present dynamics include: A worldwide chip shortage impacting industries…
21st Century Cryptography – Asynchronous ASIC | Jason Graalum, GaloisPrior to spinning out of Galois, engineers from Niobium Microsystems completed work on the 21st Century Cryptography DARPA project. This project developed a proof-of-concept ASIC containing high-performance, low-energy, side-channel…
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René Rebe Patches the Linux Kernel for “World’s First” Look at a Radeon RX 6700XT on a RISC-V PC | Gareth Halfacree, Hackster.ioComputer scientist René Rebe has patched the Linux kernel to bring support for AMD's RDNA2-based Radeon RX 6700XT graphics card to RISC-V systems — starting…
WARP-V: A RISC-V CPU Core Generator Supporting MIPS ISA | Abhishek Jadhav, CNX SoftwareIf you have been working on open standard RISC-V ISA CPU cores, there is a high chance that you have come across WARP-V. For newbies,…
Previewing the Beagle V | Mender.ioBeagleboard.org has joined forces with Seeed and StarFive to launch the Beagle V . The Beagle V has the advantage of being a low cost board that…
Imperas updates Free reference model riscvOVPsimPlus with new RISC-V P (SIMD/DSP) extension and Architectural Validation Test SuitesImperas Software Ltd., the leader in RISC-V processor verification technology, announces the latest updates to riscvOVPsimPlus with support for the near ratified P extension and architectural validation test…
Case Study: SiFive Launches Unmatched Board Remotely | Blue Clover DevicesThe Challenge A guiding light in the RISC-V community, SiFive was preparing to launch a new quad-core processor and evaluation board. Preorders were accumulating on…
RISC-V processor core for functional safety supported by development tools | electropagesWith its release of development tools for RISC-V processors, IAR Systems supports the ISO 26262 ASIL-D ready certified RISC-V processor core 'EMSA5-FS' of the Fraunhofer…
Russia’s Elbrus has a RISC-V competitor as Yadro prepares native chips for launch | Gareth Halfacree, The RegisterRussia's Yadro and subsidiary Syntacore have announced an effort to develop homegrown processors based on the free and open RISC-V architecture. A report in local…
Compsci eggheads bring OpenCL framework to RISC-V to push parallel performance | Gareth Halfacree, The RegisterA quartet of computer science boffins have showcased work on bringing the OpenCL programming framework to a wide range of RISC-V chips – improving their…
What is RISC-V? | Abhishek JadhavWhen it comes to designing your own CPU core, you primarily need to get an open-source ISA (instruction set architecture). This open-source ISA will help…
Video: Decade of RISC-V Desktop?! HiFive Unmatched First LookThe world's most powerful RISC-V development platform is here, and we are building a computer with it! This is a first look at SiFive's new…
NSITEXE achieves world’s first RISC-V processor with vector extension certified for ISO 26262 ASIL D ready product |The DR1000C, a data flow processor (DFP) developed by NSITEXE, Inc. (headquartered in Minato Ward, Tokyo, Japan; President and CEO: Yukihide Niimi; hereinafter “NSITEXE”) has…
Chinese Wearable Technology Firm Huami to Launch New OS with Better Understanding of Users | PandailyChinese smart wearable device manufacturer Zepp Health, previously known in the international market as Huami, has announced that it planned to unveil its own OS,…