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Global alliance formed to promote open hardware support for women and underrepresented individuals | Aimee Kalnoskas, EE World Online
Video: RISC-V RV32I B-Type | Maven Silicon
Developing standards-based verification environments for extensible RISC-V processor cores | Kevin McDermott, Imperas Software
PUFiot: An Essential Secure Coprocessor for RISC-V | Sam Chung, Sean H. Wu, and Evans Yang, PUF Security
Video: It’s Not Just About Embedded! | The Yocto Project
Zephyr RTOS + RISC-V – see the live demo at Open Source Summit/Embedded Linux Conference! | Jonathan Beri, Golioth
New release of SweRVolf RISC-V SoC project aims for lower barrier to entry | Gareth Halfacree, The Register
Optimization Driving Changes In Microarchitectures | Ann Steffora Mutschler, Semiconductor Engineering
RISC-V Chiplets, Disaggregated Die, and Tiles | Chris Jones, SiFive
ZAYA now supports RISC-V | Zaya
…and out come SweRVolf | Olof Kindgren, Qamcom
Open source SystemVerilog tools in ASIC design | Antmicro, Google Open Source Blog
DARPA adds RISC-V to its Toolbox: Defense researchers can get special access to SiFive chip designs | Katyanna Quach
An Ultra-Low Power RISC-V Chip and a Clever Neural Network Give This Crazyflie “Top-Notch” Autonomy | Gareth HalfacreeRISC-V Extension Boasts Dramatic Improvements in Ultra-Low Power IoT Wireless Signal Processing | Gareth Halfacree
Axiomise Unveils Formal Verification 101 Training Program | GlobeNewsWireAxiomise Unveils Formal Verification 101 Training Program | Press Release
Video: #CSWSpring21 / RISC-V for acceleration of data-parallel workloads: from IoT to HPC
First Google-Sponsored MPW Shuttle Launched at SkyWater with 40 Open Source Community Submitted Designs | Press ReleaseVideo: Multithreaded Application Synchronization pt. II (Mutual Exclusion Locks a’la RISC-V) | John’s Basement
ARM vs RISC-V Vector Extensions | Erik Engheim
Codasip to Offer Secure Boot Solutions with Veridify ToolsVideo: Verification and Virtual Prototyping for RISC-V Systems
Global alliance formed to promote open hardware support for women and underrepresented individuals | Aimee Kalnoskas, EE World OnlineRISC-V International, a global open hardware standards organization, today announced the launch of the Open Hardware Diversity Alliance. The global Alliance, created by CHIPS Alliance,…
Video: RISC-V RV32I B-Type | Maven SiliconThis video explains the RV32I B-Type instructions. To know more, explore our RISC-V courses, https://elearn.maven-silicon.com/risc-v RISC-V is growing rapidly, follow this RISC-V video…
Developing standards-based verification environments for extensible RISC-V processor cores | Kevin McDermott, Imperas SoftwareOne of the appealing things about open-source is that it invites modification to the underlying technology. In the case of the RISC-V instruction set architecture…
PUFiot: An Essential Secure Coprocessor for RISC-V | Sam Chung, Sean H. Wu, and Evans Yang, PUF SecurityThe number of connected IoT devices exceeded 46 billion in 2021 and is expected to reach a remarkable 125 billion by 2030. This will shift…
Video: It’s Not Just About Embedded! | The Yocto Project“Embedded Linux people build custom Linux systems.” Thats how things are, right? And yeah, they do that a real lot for sure. But why invest…
Zephyr RTOS + RISC-V – see the live demo at Open Source Summit/Embedded Linux Conference! | Jonathan Beri, GoliothAn Instruction Set Architecture (ISA) is like the DNA of a computer. It’s what makes Arm®-based processors Arm, x86-based CPUs Intel®, and so on. RISC-V…
New release of SweRVolf RISC-V SoC project aims for lower barrier to entry | Gareth Halfacree, The RegisterThe SweRVolf project, a fully open system-on-chip designed as a reference platform for Western Digital's RISC-V SweRV cores, has announced a major new release promising…
Optimization Driving Changes In Microarchitectures | Ann Steffora Mutschler, Semiconductor EngineeringThe semiconductor ecosystem is at a turning point for how to best architect the CPU based on the explosion of data, the increased usage of…
RISC-V Chiplets, Disaggregated Die, and Tiles | Chris Jones, SiFiveScalable High-Performance Computing SoC Design with RISC-V Whether you refer to the design concept as a disaggregated die, tiles, chiplets, or good ol’ multi-chip modules,…
ZAYA now supports RISC-V | ZayaZAYA is a secure operating system that creates a TEE (Trusted Execution Environment) to manage all sensitive operations and resources securely. ZAYA supports and follows…
…and out come SweRVolf | Olof Kindgren, QamcomOne of the main FOSSi projects I've been running the last couple of years is SweRVolf, a FuseSoC-based reference platform for Western Digital's family of RISC-V cores…
Open source SystemVerilog tools in ASIC design | Antmicro, Google Open Source BlogOpen source hardware is undeniably undergoing a renaissance whose origin can be traced to the establishment of RISC-V Foundation (later redubbed RISC-V International). The open…
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DARPA adds RISC-V to its Toolbox: Defense researchers can get special access to SiFive chip designs | Katyanna QuachEngineers and scientists working on American military research programs can now access RISC-V processor core designs and associated blueprints through DARPA's Toolbox, and use the…
An Ultra-Low Power RISC-V Chip and a Clever Neural Network Give This Crazyflie “Top-Notch” Autonomy | Gareth HalfacreeGAP8 "Parallel Ultra-Low Power" chip draws just 86mW to drive a 135 frames-per-second autonomous flight system with pose estimation. Read the full article.
RISC-V Extension Boasts Dramatic Improvements in Ultra-Low Power IoT Wireless Signal Processing | Gareth HalfacreeExtensions to the open source ISA offer "substantial energy savings" for common IoT protocols including LoRa and Bluetooth Low Energy. Read the full article.
Axiomise Unveils Formal Verification 101 Training Program | GlobeNewsWireLONDON, April 06, 2021 (GLOBE NEWSWIRE) -- Axiomise, the leading provider of cutting-edge formal verification consulting, training, services, and IP, today unveiled a comprehensive introductory certification-based…
Axiomise Unveils Formal Verification 101 Training Program | Press ReleaseCertification-Based Self-Paced On-Demand Continuing Education Program Includes Best Practices for Using Formal Verification LONDON, April 06, 2021 (GLOBE NEWSWIRE) -- Axiomise, the leading provider of cutting-edge…
Video: #CSWSpring21 / RISC-V for acceleration of data-parallel workloads: from IoT to HPCIn this talk by Luca Benini (University of Bologna / ETH Zurich), we will look into RISC-V based architectures for acceleration of data-parallel workloads. The…
First Google-Sponsored MPW Shuttle Launched at SkyWater with 40 Open Source Community Submitted Designs | Press ReleaseCollaboration among SkyWater, Efabless and Google enables industry’s first open source ASICs BLOOMINGTON, Minn. & SAN JOSE, Calif.--(BUSINESS WIRE)--SkyWater Technology, the trusted technology realization partner,…
Video: Multithreaded Application Synchronization pt. II (Mutual Exclusion Locks a’la RISC-V) | John’s BasementA look at the need for and operation of the RISC-V AMOSWAP instruction. Course web site: http://faculty.cs.niu.edu/~winans/CS463 RISC-V Instruction Set Manual: https://riscv.org/technical/specifications/ RISC-V Instruction Set…
ARM vs RISC-V Vector Extensions | Erik EngheimA comparison of the RISC-V vector extension (RVV) and ARM scalable vector extension (SVE/SVE2). Read the blog.
Codasip to Offer Secure Boot Solutions with Veridify ToolsShelton, Connecticut and Munich, Germany – March 30th, 2021 – Codasip, the leading supplier of customizable RISC-V processor IP, and Veridify Security, a leader in securing…
Video: Verification and Virtual Prototyping for RISC-V Systems#RISC-V is an innovative, open-source and increasingly widespread computer architecture that provides an independent and cost-effective alternative to major #chip manufacturers. Using formal #verification tools…