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Life in a Formal Verification Lane | Shivani Shah
Agile Analog brings analog IP to RISC-V International | Jean-Pierre Joosting, Design & Reuse
René Rebe Patches the Linux Kernel for “World’s First” Look at a Radeon RX 6700XT on a RISC-V PC | Gareth Halfacree, Hackster.io
WARP-V: A RISC-V CPU Core Generator Supporting MIPS ISA | Abhishek Jadhav, CNX Software
Previewing the Beagle V | Mender.io
What You Need to Know About Verilator Open Source Tooling | Rob Mains, CHIPS Alliance
Imperas updates Free reference model riscvOVPsimPlus with new RISC-V P (SIMD/DSP) extension and Architectural Validation Test Suites
Case Study: SiFive Launches Unmatched Board Remotely | Blue Clover Devices
RISC-V processor core for functional safety supported by development tools | electropages
Russia’s Elbrus has a RISC-V competitor as Yadro prepares native chips for launch | Gareth Halfacree, The RegisterCompsci eggheads bring OpenCL framework to RISC-V to push parallel performance | Gareth Halfacree, The Register
What is RISC-V? | Abhishek Jadhav
Here’s a new well-stocked RISC-V Raspberry Pi challenger | Mayank Sharma, TechRadar
Renode 1.11 – improved testing, RISC-V support and user experience | Zephyr Project
Zepp To Debut and Wow Consumers Worldwide at CES 2021 | PRNewswire, Zepp
Sunplus Technology Uses SiFive RISC-V Processor | 凌陽科技採用SiFive RISC-V處理器 | Digitimes (Chinese)
RISC-V and the future of open-source computing at CES 2021 | Engadget
RISC-V, a Technology That Can Change the Future of Hardware | Milagros Martinez, TekCrispy (Spanish)Aiming at Smart, Efficient, and Low-Energy IoT Scenarios, “Risechip” Develops AI Chips Based on the RISC-V Architecture | Zi Yu Qing, Sohu (Chinese)
Why Processor? | Maven Silicon – A RISC-V Training Partner | Maven Silicon
Rediscovering RISC-V: Apple M1 sparks renewed interest in non-x86 architectures | Robin Harris, Storage Bits, ZDNet
SEGGER introduces new Open Flashloader for direct programming of any RISC-V system | SEGGER
Andes Technology Provides RISC-V CPU Core to SK Telecom | Andes Technology
Life in a Formal Verification Lane | Shivani ShahThis summer, I got the opportunity to work as a Formal Verification Intern with Axiomise for six weeks. I’m a keen designer and love working…
Agile Analog brings analog IP to RISC-V International | Jean-Pierre Joosting, Design & ReuseAs a strategic member, Agile Analog expects to widen access to its application- and process-optimised analog IP for smart and IoT devices. Agile Analog, a…
René Rebe Patches the Linux Kernel for “World’s First” Look at a Radeon RX 6700XT on a RISC-V PC | Gareth Halfacree, Hackster.ioComputer scientist René Rebe has patched the Linux kernel to bring support for AMD's RDNA2-based Radeon RX 6700XT graphics card to RISC-V systems — starting…
WARP-V: A RISC-V CPU Core Generator Supporting MIPS ISA | Abhishek Jadhav, CNX SoftwareIf you have been working on open standard RISC-V ISA CPU cores, there is a high chance that you have come across WARP-V. For newbies,…
Previewing the Beagle V | Mender.ioBeagleboard.org has joined forces with Seeed and StarFive to launch the Beagle V . The Beagle V has the advantage of being a low cost board that…
What You Need to Know About Verilator Open Source Tooling | Rob Mains, CHIPS AllianceVerilator is a high performance, open source functional simulator that has gained tremendous popularity in its usage and adoption in the verification of chip design.…
Imperas updates Free reference model riscvOVPsimPlus with new RISC-V P (SIMD/DSP) extension and Architectural Validation Test SuitesImperas Software Ltd., the leader in RISC-V processor verification technology, announces the latest updates to riscvOVPsimPlus with support for the near ratified P extension and architectural validation test…
Case Study: SiFive Launches Unmatched Board Remotely | Blue Clover DevicesThe Challenge A guiding light in the RISC-V community, SiFive was preparing to launch a new quad-core processor and evaluation board. Preorders were accumulating on…
RISC-V processor core for functional safety supported by development tools | electropagesWith its release of development tools for RISC-V processors, IAR Systems supports the ISO 26262 ASIL-D ready certified RISC-V processor core 'EMSA5-FS' of the Fraunhofer…
Russia’s Elbrus has a RISC-V competitor as Yadro prepares native chips for launch | Gareth Halfacree, The RegisterRussia's Yadro and subsidiary Syntacore have announced an effort to develop homegrown processors based on the free and open RISC-V architecture. A report in local…
Compsci eggheads bring OpenCL framework to RISC-V to push parallel performance | Gareth Halfacree, The RegisterA quartet of computer science boffins have showcased work on bringing the OpenCL programming framework to a wide range of RISC-V chips – improving their…
What is RISC-V? | Abhishek JadhavWhen it comes to designing your own CPU core, you primarily need to get an open-source ISA (instruction set architecture). This open-source ISA will help…
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Here’s a new well-stocked RISC-V Raspberry Pi challenger | Mayank Sharma, TechRadarShenzhen-based open hardware vendor Seeed has announced BeagleV, a credit-card sized RISC-V single board computer (SBC) that can run Linux. BeagleV is the result of a…
Renode 1.11 – improved testing, RISC-V support and user experience | Zephyr ProjectVersion 1.11 of Antmicro’s open source Renode simulation framework is already available. As usual, the new release introduces a range of features, modifications and fixes, enabling…
Zepp To Debut and Wow Consumers Worldwide at CES 2021 | PRNewswire, ZeppLAS VEGAS, Jan. 12, 2021 /PRNewswire/ -- Zepp, a professional brand focused on digital health management, is exhibiting at CES 2021 for the first time this year. At…
Sunplus Technology Uses SiFive RISC-V Processor | 凌陽科技採用SiFive RISC-V處理器 | Digitimes (Chinese)凌陽科技表示，已成功引進由RISC-V領導廠商SiFive所提供之RISC-V處理器，並經過工程整合、通過IP與晶片驗證。 針對工業控制領域、智慧物聯網應用、與多樣化邊緣運算的各式應用場景，會因為應用場景對於計算效能需求的不同，來配置不同的處理器組態。凌陽科技智能運算專案技術總監李桓瑞博士表示，SiFive所提供之RISC-V處理器，於單一處理器叢集內，最多可提供最多八核心、外加一顆嵌入式小核的組態，除了計算效能具備高擴充性之外，同時也能處理記憶體架構快取一致性(cache coherence)，可滿足客戶應用上對計算效能的不同需求。因為更可利用SiFive Mix+Match架構，兼具非對稱多重處理(AMP)特性的嵌入式小核，來處理系統內各種即時事件或分擔節能期間的運算需求。 Read the full article
RISC-V and the future of open-source computing at CES 2021 | EngadgetWe sat down with Calista Redmond from RISC-V International, Krste Asanović from SiFive, Ted Marena of Western Digital, and Art Swift from Esperanto Technologies to…
RISC-V, a Technology That Can Change the Future of Hardware | Milagros Martinez, TekCrispy (Spanish)El procesador representa la parte más importante de cualquier equipo. Su arquitectura, en conjunto con otros elementos, determina la eficiencia, rendimiento y calidad de determinados…
Aiming at Smart, Efficient, and Low-Energy IoT Scenarios, “Risechip” Develops AI Chips Based on the RISC-V Architecture | Zi Yu Qing, Sohu (Chinese)At the moment when chips are safe, autonomous and controllable, the attention of the Chinese people, a completely open source instruction set architecture, RISC-V, which…
Why Processor? | Maven Silicon – A RISC-V Training Partner | Maven SiliconIn this video, our founder explains the reason for and importance of learning processor design, showing how we create electronic devices like smartphones using System-on-Chips.…
Rediscovering RISC-V: Apple M1 sparks renewed interest in non-x86 architectures | Robin Harris, Storage Bits, ZDNetRISC-V is, like x86 and ARM, an instruction set architecture (ISA). Unlike x86 and ARM, it is a free and open standard that anyone can…
SEGGER introduces new Open Flashloader for direct programming of any RISC-V system | SEGGERSEGGER just released a new Open Flashloader for RISC-V systems. The template, which can be adjusted to fit any RISC-V system, allows engineers to write…
Andes Technology Provides RISC-V CPU Core to SK Telecom | Andes TechnologyHSINCHU, TAIWAN , Jan. 06, 2021 (GLOBE NEWSWIRE) -- Andes Technology Corp. today announced that its 64-bit AndesCore™ AX25 RISC-V processor has been adopted by…