Monheim am Rhein & Munich, Germany – June 22nd, 2021 – SEGGER and Codasip announce that SEGGER’s J-Link debug probes and its Embedded Studio IDE…

June 22 (Reuters) - SiFive Inc on Tuesday released a new computing chip design that aims to challenge Arm Ltd's dominance in smartphone chips and…

This summer, I got the opportunity to work as a Formal Verification Intern with Axiomise for six weeks. I’m a keen designer and love working…

x86 or x86-64 is the name of the architecture used by Intel and AMD to make their processors. RISC-V is a relatively new architecture that,…

Today's RISC-V microcontrollers may lead to future RISC-V phones and laptops. Today, RISC-V CPU design company SiFive launched a new processor family with two core…

LEMONT, Ill., OAK RIDGE, Tenn., and EDINBURGH, England, June 17, 2021 — Argonne National Laboratory (Argonne) in collaboration with Oak Ridge National Laboratory (ORNL), has…

SEGGER and Codasip announce that SEGGER’s J-Link debug probes and its Embedded Studio IDE fully support Codasip’s RISC-V processors, right out-of-the-box. SEGGER’s J-Link debug probe…

The semiconductor division of Chinese tech giant Alibaba Group announced on Tuesday that its self-developed Xuantie embedded central processing unit (CPU) has made technological breakthroughs…

GOTHENBURG, Sweden -- December 7, 2020 -- RISC-V international members SYSGO and Cobham Gaisler, the design center of Cobham Advanced Electronic Solutions (CAES), have announced their…

Sophia-Antipolis, France – Monday, December 7, 2020 – Menta S.A.S, a premier supplier of embedded FPGA (eFPGA) solutions, today announced its close collaboration with Codasip, a leading supplier of processing solutions…

GOTHENBURG, Sweden, 7 December 2020  RISC-V international members SYSGO and Cobham Gaisler, the design center of Cobham Advanced Electronic Solutions (CAES), have announced their collaboration…

SOPHIA-ANTIPOLIS, FRANCE – December 7, 2020 – Menta S.A.S, a premier supplier of embedded FPGA (eFPGA) solutions, today announced a technology IP cooperation with Andes Technology,…

Xobs, one of the lead engineers behind the Precursor project, at the last Hackaday Superconference - back in the seemingly distant past when we still had in-person…

Munich, Germany – December 4th, 2020 – Codasip, the leading supplier of customizable RISC-V® processor IP, today announces three new 64-bit RISC-V application processor cores: the A70XP™ provides support…

Michael Gielda of Antmicro and the CHIPS Alliance! Listen to the podcast.]]>

Micro Magic Inc.—a small electronic design firm in Sunnyvale, California—has produced a prototype CPU that is several times more efficient than world-leading competitors, while retaining reasonable…

riscvOVPsimPlus™ includes latest reference model and now offers expanded simulation features for debug & trace for early software development and hardware verification. Oxford, UK –…

keynote session including our partners and RISC-V International members, and giving talks describing our efforts aimed at improving the RISC-V tooling ecosystem. Read the full article.]]>

PULP Platform The Parallel Ultra Low Power (PULP) Platform started as a joint effort between the Integrated Systems Laboratory (IIS) of ETH Zürich and the…