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SiFive aims to challenge Arm with new tech, pairs with Intel on effort | Stephen Nellis, Reuters
Life in a Formal Verification Lane | Shinavi Shah, SemiWiki.com
Video: RISC-V vs x86 – History and Key Differences Explained
SiFive’s brand-new P550 is one of the world’s fastest RISC-V CPUs | Jim Salter, arsTechnica
Argonne, ORNL Award Codeplay Contract to Strengthen SYCL Support for AMD GPUs | HPCwire
SEGGER and Codasip Announce Cooperation on RISC-V
Alibaba’s chip unit realizes key breakthroughs with Xuantie CPU | Global Times
RISC-V could be coming to supercomputers (eventually) | Brad Linder, liliputing
Porting PikeOS to NOEL-V and LEON: SYSGO and Cobham Gaisler Extend Cooperation around RISC-V | Design & Reuse
Menta eFPG and Codasip Announce Technology Partnership | Codasip
Porting PikeOS to NOEL-V and LEON: SYSGO and Cobham Gaisler Extend Cooperation around RISC-V | Cobham
Menta and Andes Announce Partnership Enabling Hardware Reconfiguring for ISA Extension | Andes Technology
Betrusted’s Precursor and Renode – a user story | Antmicro
Codasip Announces Three New RISC-V Application Processor Cores Providing Multi-Core and SIMD Capability | Codasip
#519 – Simulating Embedded Hardware with Michael Gielda | The AMP Hour
New RISC-V CPU claims record breaking performance per watt | Micro Magic Inc
Imperas Extends free riscvOVPsimPlus Simulator for RISC-V | Imperas
RISC-V Summit 2020 – virtual booth, keynote session and talks | Antmicro
RISC-V for ultra-low power processing and AI on the edge | Jeff Shepard, Microcontroller Tips
SiFive aims to challenge Arm with new tech, pairs with Intel on effort | Stephen Nellis, ReutersJune 22 (Reuters) - SiFive Inc on Tuesday released a new computing chip design that aims to challenge Arm Ltd's dominance in smartphone chips and…
Life in a Formal Verification Lane | Shinavi Shah, SemiWiki.comThis summer, I got the opportunity to work as a Formal Verification Intern with Axiomise for six weeks. I’m a keen designer and love working…
Video: RISC-V vs x86 – History and Key Differences Explainedx86 or x86-64 is the name of the architecture used by Intel and AMD to make their processors. RISC-V is a relatively new architecture that,…
SiFive’s brand-new P550 is one of the world’s fastest RISC-V CPUs | Jim Salter, arsTechnicaToday's RISC-V microcontrollers may lead to future RISC-V phones and laptops. Today, RISC-V CPU design company SiFive launched a new processor family with two core…
Argonne, ORNL Award Codeplay Contract to Strengthen SYCL Support for AMD GPUs | HPCwireLEMONT, Ill., OAK RIDGE, Tenn., and EDINBURGH, England, June 17, 2021 — Argonne National Laboratory (Argonne) in collaboration with Oak Ridge National Laboratory (ORNL), has…
SEGGER and Codasip Announce Cooperation on RISC-VSEGGER and Codasip announce that SEGGER’s J-Link debug probes and its Embedded Studio IDE fully support Codasip’s RISC-V processors, right out-of-the-box. SEGGER’s J-Link debug probe…
Alibaba’s chip unit realizes key breakthroughs with Xuantie CPU | Global TimesThe semiconductor division of Chinese tech giant Alibaba Group announced on Tuesday that its self-developed Xuantie embedded central processing unit (CPU) has made technological breakthroughs…
RISC-V could be coming to supercomputers (eventually) | Brad Linder, liliputingRISC-V chips like the processors are starting to show up in low-power, open source computers like the HiFive Unmatched and Nezha as well as educational products like the BBC Doctor…
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Porting PikeOS to NOEL-V and LEON: SYSGO and Cobham Gaisler Extend Cooperation around RISC-V | Design & ReuseGOTHENBURG, Sweden -- December 7, 2020 -- RISC-V international members SYSGO and Cobham Gaisler, the design center of Cobham Advanced Electronic Solutions (CAES), have announced their…
Menta eFPG and Codasip Announce Technology Partnership | CodasipSophia-Antipolis, France – Monday, December 7, 2020 – Menta S.A.S, a premier supplier of embedded FPGA (eFPGA) solutions, today announced its close collaboration with Codasip, a leading supplier of processing solutions…
Porting PikeOS to NOEL-V and LEON: SYSGO and Cobham Gaisler Extend Cooperation around RISC-V | CobhamGOTHENBURG, Sweden, 7 December 2020 RISC-V international members SYSGO and Cobham Gaisler, the design center of Cobham Advanced Electronic Solutions (CAES), have announced their collaboration…
Menta and Andes Announce Partnership Enabling Hardware Reconfiguring for ISA Extension | Andes TechnologySOPHIA-ANTIPOLIS, FRANCE – December 7, 2020 – Menta S.A.S, a premier supplier of embedded FPGA (eFPGA) solutions, today announced a technology IP cooperation with Andes Technology,…
Betrusted’s Precursor and Renode – a user story | AntmicroXobs, one of the lead engineers behind the Precursor project, at the last Hackaday Superconference - back in the seemingly distant past when we still had in-person…
Codasip Announces Three New RISC-V Application Processor Cores Providing Multi-Core and SIMD Capability | CodasipMunich, Germany – December 4th, 2020 – Codasip, the leading supplier of customizable RISC-V® processor IP, today announces three new 64-bit RISC-V application processor cores: the A70XP™ provides support…
#519 – Simulating Embedded Hardware with Michael Gielda | The AMP HourMichael Gielda of Antmicro and the CHIPS Alliance! Listen to the podcast.]]>
New RISC-V CPU claims record breaking performance per watt | Micro Magic IncMicro Magic Inc.—a small electronic design firm in Sunnyvale, California—has produced a prototype CPU that is several times more efficient than world-leading competitors, while retaining reasonable…
Imperas Extends free riscvOVPsimPlus Simulator for RISC-V | ImperasriscvOVPsimPlus™ includes latest reference model and now offers expanded simulation features for debug & trace for early software development and hardware verification. Oxford, UK –…
RISC-V Summit 2020 – virtual booth, keynote session and talks | Antmicrokeynote session including our partners and RISC-V International members, and giving talks describing our efforts aimed at improving the RISC-V tooling ecosystem. Read the full article.]]>
RISC-V for ultra-low power processing and AI on the edge | Jeff Shepard, Microcontroller TipsPULP Platform The Parallel Ultra Low Power (PULP) Platform started as a joint effort between the Integrated Systems Laboratory (IIS) of ETH Zürich and the…