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A first look at Allwinner D1 Linux RISC-V SBC and Processor | Jean-Luc Aufranc, CNX Soft
Homebrew RISC-V Computer Has Beauty and Brains | Tom Nardi, Hackaday
Low-Cost Single-Board Computers with RISC-V Chips are Coming Soon | Brad Linder, liliputing
Video: The Future of RISC-V in HPC – Vadim Malenboim, Sr Field Application Engineer, SiFive Core IP
SiFive Tapes Out First 5nm TSMC RISC-V Chip With 7.2 Gbps HBM3 | Anton Shilov, Tom’s Hardware
From NIST to RISC-V: PQShield continues its leading role in international cryptography standardisation efforts for software and hardware | Dr Ali El Kaafarani
Building security into an AI SoC using CPU features with extensions | Marco Ciaffi, John Min, Embedded
ESP32-C6 WiFI 6 and Bluetooth 5 LE RISC-V SoC for IoT devices coming soon | JEAN-LUC AUFRANC (CNXSOFT)
New Part Day: Espressif Esp32-C6 Includes Wifi 6 and a RISC-V Core | Kerry Scharfglass, Hackaday
Video: Pipelining of RISC-V processor
Video: Stall vs. Flush in RISC-V processor
Xen releases a new version 4.15 after a slightly delayed development process | Simon Sharwood, APAC Editor, The Register
Linux 5.10: Reveals Big Step Forward for RISC-V | Isaac, Linux Addicts (Spanish)
Arm and RISC-V Software Development Solution from Ashling: RiscFree™ for Arm & RISC-V | Ashling (Press Release)
A first look at Allwinner D1 Linux RISC-V SBC and Processor | Jean-Luc Aufranc, CNX SoftLast year, we reported that Allwinner was working on an Alibaba XuanTie C906 based RISC-V processor that would be found in low-cost Linux capable single…
Homebrew RISC-V Computer Has Beauty and Brains | Tom Nardi, HackadayBuilding your own CPU is arguably the best way to truly wrap your head around how all those ones and zeros get flung around inside…
Low-Cost Single-Board Computers with RISC-V Chips are Coming Soon | Brad Linder, liliputingThe first single-board computers powered by an Allwinner Xuantie-C906 processor could be set to ship soon. The chip isn’t exactly a speed demon, but it…
Video: The Future of RISC-V in HPC – Vadim Malenboim, Sr Field Application Engineer, SiFive Core IPRISC-V Architecture is widely adopted in the embedded and IoT market. The next phase of RISC-V Architecture evolution is the HPC segment. The SiFive portfolio…
SiFive Tapes Out First 5nm TSMC RISC-V Chip With 7.2 Gbps HBM3 | Anton Shilov, Tom’s HardwareSiFive and OpenFive hit 5nm milestone. SiFive on Tuesday said that that its OpenFive division has successfully taped out the company's first system-on-chip (SoC) on TSMC's N5…
From NIST to RISC-V: PQShield continues its leading role in international cryptography standardisation efforts for software and hardware | Dr Ali El KaafaraniPQShield announces appointment of Ben Marshall, editor and main author of the RISC-V “K’ Cryptography Extension, to bolster its hardware division PQShield, the cybersecurity company…
Building security into an AI SoC using CPU features with extensions | Marco Ciaffi, John Min, EmbeddedWith the rapid deployment of artificial intelligence (AI), the focus of AI system on chip (SoC) design has been on building smarter, faster and cheaper…
ESP32-C6 WiFI 6 and Bluetooth 5 LE RISC-V SoC for IoT devices coming soon | JEAN-LUC AUFRANC (CNXSOFT)Espressif Systems introduced their first RISC-V wireless SoC last year with ESP32-C3 single-core 32-bit RISC-V SoC offering both 2.4GHz WiFi 4 and Bluetooth 5.0 LE…
New Part Day: Espressif Esp32-C6 Includes Wifi 6 and a RISC-V Core | Kerry Scharfglass, HackadayIf you’re a reader of Hackaday, then you’ve almost certainly encountered an Espressif part. The twin microcontroller families ESP8266 and ESP32 burst onto the scene…
Video: Pipelining of RISC-V processorThis is a short discussion of the concept of "pipelining" of RISC-V processor. It was created to supplement the lectures of a course focused on…
Video: Stall vs. Flush in RISC-V processorThis is a short discussion of the concept of "pipelining" of RISC-V processor. It was created to supplement the lectures of a course focused on…
Xen releases a new version 4.15 after a slightly delayed development process | Simon Sharwood, APAC Editor, The RegisterThe Xen project has released another upgrade to its open source hypervisor. Development of this new cut – version 4.15 – proved a little trickier…
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Linux 5.10: Reveals Big Step Forward for RISC-V | Isaac, Linux Addicts (Spanish)Read the full article (Spanish).]]>
Arm and RISC-V Software Development Solution from Ashling: RiscFree™ for Arm & RISC-V | Ashling (Press Release)Read the full press release.]]>
