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[VIDEO] The Future of Compute
Box64 初步支持 RISC-V Vector 1.0 (RVV) 扩展，最高 300% 性能提升，代码已开源并合入上游（upstream）
Codeplay Brings RISC-V Support to the oneAPI Construction KitRISC-V is Built for Artificial Intelligence and SiFive Solutions for AISiFive unveils RISC-V chip design for high-performance AI workloads
[VIDEO] RISC-V Taipei Day 2024 – Reshape the Future with AI
VyperCore plans 5nm RISC-V server chip and cardBitluni’s Magnetic LED Matrix Build Showcases Clever RISC-V ProgrammingHow RISC-V Changes the Global Landscape of AI and MLSiFive Highlights Key Inflection Points Driving RISC-V Adoption for AI and Introduces Intelligence XM Series for AI Workload Acceleration
Accelerating RISC-V Processor Verification: A Co-Simulation StrategyLauterbach adds debug and trace support for Renesas 32-bit-RISC-V microcontrollers
Privileged Specification Version 1.12 Now Open to Public Review
Developing standards-based verification environments for extensible RISC-V processor cores | Kevin McDermott, Imperas Software
…and out come SweRVolf | Olof Kindgren, Qamcom
LAST CHANCE TO SUBMIT YOUR TALK TO THE 2021 RISC-V SUMMIT!RISC-V Cryptography Extensions Task Group Announces Public Review of the Scalar Cryptography Extensions
Google Summer of Code’21 at FOSSi Foundation: TensorCore Extension for Deep Learning | Nitin Mishra
Open source custom GitHub Actions runners with Google Cloud and Terraform | AntmicroGoogle Summer of Code’21 at FOSSI Foundation: M-extension Support for SERV | Zeeshan Rafique, RISC-V Ambassador
RISC-V RV32I R-Type | Maven SiliconAnnouncing public review for RISC-V standard extensions Zfinx, Zdinx, Zhinx, and Zhinxmin
StarFive open source single board hardware platform will be officially released by the end of Q3 2021
seL4 Integrity Enforcement Proved for RISC-V
Privileged Specification Version 1.12 Now Open to Public ReviewDeveloping standards-based verification environments for extensible RISC-V processor cores | Kevin McDermott, Imperas Software…and out come SweRVolf | Olof Kindgren, QamcomLAST CHANCE TO SUBMIT YOUR TALK TO THE 2021 RISC-V SUMMIT!RISC-V Cryptography Extensions Task Group Announces Public Review of the Scalar Cryptography ExtensionsGoogle Summer of Code’21 at FOSSi Foundation: TensorCore Extension for Deep Learning | Nitin MishraOpen source custom GitHub Actions runners with Google Cloud and Terraform | AntmicroGoogle Summer of Code’21 at FOSSI Foundation: M-extension Support for SERV | Zeeshan Rafique, RISC-V AmbassadorRISC-V RV32I R-Type | Maven SiliconAnnouncing public review for RISC-V standard extensions Zfinx, Zdinx, Zhinx, and ZhinxminStarFive open source single board hardware platform will be officially released by the end of Q3 2021seL4 Integrity Enforcement Proved for RISC-V
Eight core RISC-V processor and TSN switch for AI space designsMicrochip starts 64bit PIC64 family with RISC-VRISC-V Thrives Through Research, International CollaborationStealth startup Vybium developing European RISC-V AI accelerator
[VIDEO] M5: RISC-V Instruction Set Architecture | RISC CPU Performance ExplainedDAC 61: EDA addressing growing system complexity
Introducing the Mini-ITX motherboard ‘Milk-V Jupiter’ equipped with a RISC-V processorDesk of Ladyada – It’s a RISC-V kinda weekend #DeskOfLadyada #Adafruit
RISC-V Summit Europe 2024[VIDEO] RISC-V NAS: BPI-F3 & OpenMediaVault
Sunny skies and electric energy: RISC-V Summit Europe 2024 shines in MunichRISC-V Summit Europe News—Processor IP, Verification Tools, and More
[VIDEO] The Future of ComputePatrick Little, SiFive Chairman, President and CEO talks about how RISC-V is shaping the future of compute, how SiFive is gaining momentum from applications from…
Box64 初步支持 RISC-V Vector 1.0 (RVV) 扩展，最高 300% 性能提升，代码已开源并合入上游（upstream）Box64 RISC-V 后端使用标量指令模拟实现了 MMX、SSE* 等 x86_64 向量扩展，实现了对于 rv64gc 的良好兼容性，但一条向量指令往往需要十几条甚至几十条标量指令才能模拟，因此，对于大量使用向量指令的 x86_64 程序，Box64 的性能损失相对较大。 近日，来自 PLCT Lab 的开发人员为 Box64 RISC-V 后端新增了初步的 RVV 1.0 支持，提交相关 PR 30 余个，目前已经支持了百余条…
Codeplay Brings RISC-V Support to the oneAPI Construction KitRISC-V is the fast growing, open standard instruction set architecture (ISA) for processors of all types including CPUs and accelerators. These processors can be utilized…
RISC-V is Built for Artificial Intelligence and SiFive Solutions for AIRISC-V inventor and SiFive Founder Krste Asanovic discusses why RISC-V is "built for" AI applications and how SiFive is working from the edge to the…
SiFive unveils RISC-V chip design for high-performance AI workloadsSiFive, a designer of chips based on the RISC-V computing platform, announced a series of new AI chips for high-performance AI workloads. The SiFive Intelligence…
[VIDEO] RISC-V Taipei Day 2024 – Reshape the Future with AIThe development of AI computing has reached a critical inflexion point. Large-language models (LLMs) have attracted tremendous attention recently and require huge computations for AI…
VyperCore plans 5nm RISC-V server chip and cardVyperCore in Bristol is aiming to design and sell a 5nm chip and card for the server market to accelerate existing software. For this, VyperCore…
Bitluni’s Magnetic LED Matrix Build Showcases Clever RISC-V ProgrammingYouTuber bitluni's latest incredible build video uses a RISC-V microcontroller with an uncommon driving technique to create a modular magnetic LED matrix. The LED matrix is…
How RISC-V Changes the Global Landscape of AI and MLThe rise of Artificial Intelligence (AI) and Machine Learning (ML) has rapidly impacted today's global economy, influencing everything from healthcare to autonomous systems. As of…
SiFive Highlights Key Inflection Points Driving RISC-V Adoption for AI and Introduces Intelligence XM Series for AI Workload AccelerationSanta Clara, Calif. – Sept. 18, 2024 – Today, SiFive, Inc. the gold standard for RISC-V computing, announced the SiFive Intelligence™ XM Series designed for accelerating high…
Accelerating RISC-V Processor Verification: A Co-Simulation StrategyWith RISC-V processor architectures gaining traction across diverse computing systems, ensuring their reliability through rigorous verification becomes more crucial than ever. We have embraced a…
Lauterbach adds debug and trace support for Renesas 32-bit-RISC-V microcontrollersLauterbach's TRACE32® development tools now provide support for Renesas’s primary 32-bit RISC-V® general-purpose Microcontroller family, designed for cost-conscious and energy-efficient embedded applications. In addition to…
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Privileged Specification Version 1.12 Now Open to Public ReviewWe are delighted to announce that several specifications have been opened to public review. All of these specifications add functionality to the RISC-V Privileged Specification.…
Developing standards-based verification environments for extensible RISC-V processor cores | Kevin McDermott, Imperas SoftwareOne of the appealing things about open-source is that it invites modification to the underlying technology. In the case of the RISC-V instruction set architecture…
…and out come SweRVolf | Olof Kindgren, QamcomOne of the main FOSSi projects I've been running the last couple of years is SweRVolf, a FuseSoC-based reference platform for Western Digital's family of RISC-V cores…
LAST CHANCE TO SUBMIT YOUR TALK TO THE 2021 RISC-V SUMMIT!Time is running out! The Call for Papers is open until Friday, September 10 at 11:59 pm PST. (Yes - TOMORROW!) Don't miss your opportunity…
RISC-V Cryptography Extensions Task Group Announces Public Review of the Scalar Cryptography ExtensionsThe Cryptography Extensions Task Group is delighted to announce the start of the public review period for the RISC-V Scalar Cryptography extensions. The RISC-V Scalar…
Google Summer of Code’21 at FOSSi Foundation: TensorCore Extension for Deep Learning | Nitin MishraIntroduction This has been a great summer! I was fortunate enough to be accepted into the Google Summer Code(GSOC) program for the “TensorCore Extension for…
Open source custom GitHub Actions runners with Google Cloud and Terraform | AntmicroAs we continue our push for more software-driven hardware development as part of our work within CHIPS Alliance and RISC-V, we see an increasing need…
Google Summer of Code’21 at FOSSI Foundation: M-extension Support for SERV | Zeeshan Rafique, RISC-V AmbassadorThis project aims to design and integrate the integer “Multiplication and Division Unit (MDU)” with SERV core as a co-processor. The MDU will support all…
RISC-V RV32I R-Type | Maven SiliconThis video explains the RV32I R-Type instructions. RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats,…
Announcing public review for RISC-V standard extensions Zfinx, Zdinx, Zhinx, and ZhinxminThe RISC-V Zfinx Task Group is thrilled to announce the Zfinx extension (pronounced “z-f-in-x”) has entered the public review period. The Zfinx extension brings the…
StarFive open source single board hardware platform will be officially released by the end of Q3 2021At Starfive Technology, we have been committed to promoting the development of the global RISC-V open source software and hardware ecosystem since we were founded.…
seL4 Integrity Enforcement Proved for RISC-VThe seL4 Foundation and RISC-V International are pleased to announce that Ryan Barry from UNSW Sydney has completed the proof that the seL4 microkernel on…
No recent posts listed
Privileged Specification Version 1.12 Now Open to Public ReviewWe are delighted to announce that several specifications have been opened to public review. All of these specifications add functionality to the RISC-V Privileged Specification.…
Developing standards-based verification environments for extensible RISC-V processor cores | Kevin McDermott, Imperas SoftwareOne of the appealing things about open-source is that it invites modification to the underlying technology. In the case of the RISC-V instruction set architecture…
…and out come SweRVolf | Olof Kindgren, QamcomOne of the main FOSSi projects I've been running the last couple of years is SweRVolf, a FuseSoC-based reference platform for Western Digital's family of RISC-V cores…
LAST CHANCE TO SUBMIT YOUR TALK TO THE 2021 RISC-V SUMMIT!Time is running out! The Call for Papers is open until Friday, September 10 at 11:59 pm PST. (Yes - TOMORROW!) Don't miss your opportunity…
RISC-V Cryptography Extensions Task Group Announces Public Review of the Scalar Cryptography ExtensionsThe Cryptography Extensions Task Group is delighted to announce the start of the public review period for the RISC-V Scalar Cryptography extensions. The RISC-V Scalar…
Google Summer of Code’21 at FOSSi Foundation: TensorCore Extension for Deep Learning | Nitin MishraIntroduction This has been a great summer! I was fortunate enough to be accepted into the Google Summer Code(GSOC) program for the “TensorCore Extension for…
Open source custom GitHub Actions runners with Google Cloud and Terraform | AntmicroAs we continue our push for more software-driven hardware development as part of our work within CHIPS Alliance and RISC-V, we see an increasing need…
Google Summer of Code’21 at FOSSI Foundation: M-extension Support for SERV | Zeeshan Rafique, RISC-V AmbassadorThis project aims to design and integrate the integer “Multiplication and Division Unit (MDU)” with SERV core as a co-processor. The MDU will support all…
RISC-V RV32I R-Type | Maven SiliconThis video explains the RV32I R-Type instructions. RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats,…
Announcing public review for RISC-V standard extensions Zfinx, Zdinx, Zhinx, and ZhinxminThe RISC-V Zfinx Task Group is thrilled to announce the Zfinx extension (pronounced “z-f-in-x”) has entered the public review period. The Zfinx extension brings the…
StarFive open source single board hardware platform will be officially released by the end of Q3 2021At Starfive Technology, we have been committed to promoting the development of the global RISC-V open source software and hardware ecosystem since we were founded.…
seL4 Integrity Enforcement Proved for RISC-VThe seL4 Foundation and RISC-V International are pleased to announce that Ryan Barry from UNSW Sydney has completed the proof that the seL4 microkernel on…
Eight core RISC-V processor and TSN switch for AI space designsMicrochip is qualifying an eight core fault tolerant RISC-V processor for AI in space applications. The radiation tolerant PIC64-HSPC octal core 1.2GHz switch provides 26K…
Microchip starts 64bit PIC64 family with RISC-VMicrochip has launched its first 64bit microprocessor line, starting with a multicore RISC-V cluster for its PIC64GX family. The PIC64 GX1000 uses the existing RISC-V…
RISC-V Thrives Through Research, International CollaborationMunich, Germany — During the recent RISC-V Summit Europe, EE Times had the opportunity to talk to a leading RISC-V researcher Frank Kagan Gürkaynak, a…
Stealth startup Vybium developing European RISC-V AI acceleratorEuropean startup Vybium is developing am AI accelerator chip using the open RISC-V instruction set architecture to take on the Nvidia A100 GPU in the…
[VIDEO] M5: RISC-V Instruction Set Architecture | RISC CPU Performance ExplainedIn this course, our Founder and CEO, Mr. P R Sivakumar, explains the layered architecture of RISC-V open ISA and how we chip designers design…
DAC 61: EDA addressing growing system complexityAt this year’s Design Automation Conference (DAC), I was told that the committee had received some 1,500 technical paper and presentation submissions, and a 34%…
Introducing the Mini-ITX motherboard ‘Milk-V Jupiter’ equipped with a RISC-V processorMilk-V , a developer of RISC-V-related hardware, has announced the Milk-V Jupiter, a Mini-ITX motherboard equipped with a RISC-V processor. Milk-V Jupiter | RISC-V PC…
Desk of Ladyada – It’s a RISC-V kinda weekend #DeskOfLadyada #AdafruitThis weekend we ended up working a lot on two RISC-V designs in a push to get the final PCBs out the door. First up…
RISC-V Summit Europe 2024Germany was buzzing this week. No, not because of the Euros. Munich also hosted the 2024 edition of the RISC-V Summit Europe, and Codethink was…
[VIDEO] RISC-V NAS: BPI-F3 & OpenMediaVaultRAID RISC-V NAS built using a Banana Pi BPI-F3 single board computer and a JMB582 PCIe to SATA adapter. Watch the video.
Sunny skies and electric energy: RISC-V Summit Europe 2024 shines in MunichThis week, the 2024 edition of RISC-V Summit Europe took place in lovely Munich, Germany. Those of us who attended last year’s edition in Barcelona…
RISC-V Summit Europe News—Processor IP, Verification Tools, and MoreAt every point in the design process, RISC-V developers can make use of the advancements presented at RISC-V Summit Europe. It’s been a big week…