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Renode 1.13 for improved machine learning and pre-silicon development | Antmicro
Thermal (IR) Imaging Pipeline (ISP) Core on PolarFire® SoC FPGA SoM | Microchip
XuanTie C906 Tops MLPerf Tiny v0.7 Benchmark | MengChang, Alibaba Cloud
Why MIPS is Betting Big on RISC-V: Q&A with RISC-V International and MIPS | MIPS
RISC-V Summit China 2022 Call for Talks is Now OpenSimplifying the Vehicle to Anything (V2X) Journey: Porting of Jamaica VM on PolarFire® SoC Icicle Kit | Leah Iris, MicrochipMIPS Pivots to RISC-V with Best-In-Class Performance and Scalability | MIPS
E4 Computer Engineering joins RISC-V International | E4 Computer Engineering
RISC-V Open Era of Computing – A Conversation with Calista Redmond and Mr. Sivakumar P R , Founder and CEO of Maven Silicon | Maven Silicon
Join us in the classroom! Put RISC-V into your Computer Architecture course using RVfpga! | Robert C.W. Owen, Imagination TechnologiesAlibaba Cloud Tops MLPerf Tiny v0.7 Benchmark | Alibaba CloudXuantie IOMMU from T-Head for RISC-V | Chong Ren, Alibaba Cloud
Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT project
Opening Up New Design Possibilities with OmniXtend
The Cybersecurity Pincushion and a Myriad of Tiny Threat Points
Check out the new RISC-V Careers page and RISC-V Mentorship program!
FOSSi Fever 2020
RISC-V Security Forum 2021 – Schedule Announced!
Growing an Open and Inclusive Community
RISC-V Execution Stages | Maven Silicon
RISC-V Star Rising from the East – Introducing StarFive
RISC-V growth and successes in technology and industry : embedded world 2021
OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IP
RISC-V Becoming Less Risky with the Right Verification
Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT projectOpening Up New Design Possibilities with OmniXtendThe Cybersecurity Pincushion and a Myriad of Tiny Threat PointsCheck out the new RISC-V Careers page and RISC-V Mentorship program!FOSSi Fever 2020RISC-V Security Forum 2021 – Schedule Announced!Growing an Open and Inclusive CommunityRISC-V Execution Stages | Maven SiliconRISC-V Star Rising from the East – Introducing StarFiveRISC-V growth and successes in technology and industry : embedded world 2021OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IPRISC-V Becoming Less Risky with the Right Verification
Renode 1.13 for improved machine learning and pre-silicon development | AntmicroAfter a longer while, we are excited to announce that the next release of Renode is here. Since the previous release we’ve been busy working with many…
Thermal (IR) Imaging Pipeline (ISP) Core on PolarFire® SoC FPGA SoM | MicrochipOur Mi-V partner, Digital Core Technologies (DCT), has developed a thermal Imaging Pipeline on PolarFire® SoC FPGA. The thermal Image Signal Processor (ISP) is an…
XuanTie C906 Tops MLPerf Tiny v0.7 Benchmark | MengChang, Alibaba CloudXuanTie C906 is a processor developed by Alibaba Cloud based on the RISC-V instruction set architecture. It has attained top marks in the most recent…
Why MIPS is Betting Big on RISC-V: Q&A with RISC-V International and MIPS | MIPSMIPS recently announced that the company is pivoting to RISC-V and introduced its first MIPS products based on RISC-V, targeting automotive, 5G and wireless networking,…
RISC-V Summit China 2022 Call for Talks is Now OpenThe RISC-V Summit China 2022 will showcase the continued rapid expansion of the RISC-V ecosystem, with both commercial offerings and exciting open-source developments. The event will…
Simplifying the Vehicle to Anything (V2X) Journey: Porting of Jamaica VM on PolarFire® SoC Icicle Kit | Leah Iris, MicrochipIndustries like manufacturing and automotive are facing the challenges of getting access to device-wide data, analyzing useful data and combining and processing data in the…
MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability | MIPSMIPS previews the first IP solutions in the eVocore™ product lineup: P8700 and I8500 multiprocessors. SAN JOSE, Calif., May 10, 2022 /PRNewswire/ -- MIPS, a leading developer of…
E4 Computer Engineering joins RISC-V International | E4 Computer EngineeringThe company aims to promote the development and application of the RISC-V open standard in ecosystems for HPC applications. Scandiano (RE), May 3rd 2022…
RISC-V Open Era of Computing – A Conversation with Calista Redmond and Mr. Sivakumar P R , Founder and CEO of Maven Silicon | Maven SiliconIndia’s top VLSI Training Services company Maven Silicon, a RISC-V Global Training Partner, conducted an insightful discussion with the industry experts Ms. Calista Redmond, CEO,…
Join us in the classroom! Put RISC-V into your Computer Architecture course using RVfpga! | Robert C.W. Owen, Imagination TechnologiesDear Professors and Friends, Online is convenient and it has saved us during the pandemic, but you can't beat in-person class! That immersive feeling of…
Alibaba Cloud Tops MLPerf Tiny v0.7 Benchmark | Alibaba CloudAlibaba Cloud’s Xuantie C906 processor attained firsts in the most recent findings from MLPerf Tiny v0.7, an AI benchmark focusing on IOT devices. The Xuantie…
Xuantie IOMMU from T-Head for RISC-V | Chong Ren, Alibaba CloudThe recent development of the RISC-V IOMMU effort has attracted substantial attention from the RISC-V community. Xuantie IOMMU from T-Head Semiconductors of Alibaba Group, holding…
No recent posts listed
Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT projectThe EU-funded Very Efficient Deep Learning in IoT (VEDLIoT) project is underway. Launched at the end of 2020, it aims to build a next-generation IoT…
Opening Up New Design Possibilities with OmniXtendI am thrilled to see the announcement and initiation of collaboration between CHIPS Alliance and RISC-V International on the OmniXtend Cache Coherency protocol. We have…
The Cybersecurity Pincushion and a Myriad of Tiny Threat Points“Large organizations are using over 130 tools on average. This is just massive!” - Matt Chiodi, CSO, Palo Alto Networks’ public cloud A new Cloud…
Check out the new RISC-V Careers page and RISC-V Mentorship program!We are excited to announce the new RISC-V Careers page and RISC-V Mentorship program! As the RISC-V ecosystem and community grow, we’re bringing together those…
FOSSi Fever 20202020 was a year with a lot of bad news and so it feels slightly strange to cheerfully write about a very specific topic in…
RISC-V Security Forum 2021 – Schedule Announced!The RISC-V Forums, hosted by RISC-V International, are short-form, single-topic, deep-dive virtual events. This is the spirit of RISC-V events - providing technical content to…
Growing an Open and Inclusive CommunityCollaboration underpins everything we do in the RISC-V community. That’s why we encourage everyone to join us and participate, and why we are working hard…
RISC-V Execution Stages | Maven SiliconThis video explains the execution stages of a RISC-V processor and how it executes all the instructions. Follow this RISC-V video blog series to obtain…
RISC-V Star Rising from the East – Introducing StarFiveWith the recent announcement of BeagleVTM, reported by premium technology media Ars Technica, Tom’s Hardware, CNX Software, as well as many others, a new name…
RISC-V growth and successes in technology and industry : embedded world 2021RISC-V International has more than 1,000 members across over 50 countries who are working in hardware, software, services, and various industries for a strong and…
OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IPThe RISC-V ISA (Instruction Set Architecture) permits a range of possibilities for processor implementation with a modular approach for standard and custom extensions. In addition,…
RISC-V Becoming Less Risky with the Right VerificationRISC-V continues to make headlines across the electronic design industry. You may have seen the recent news that the OpenHW Group is delivering their first…
No recent posts listed
Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT projectThe EU-funded Very Efficient Deep Learning in IoT (VEDLIoT) project is underway. Launched at the end of 2020, it aims to build a next-generation IoT…
Opening Up New Design Possibilities with OmniXtendI am thrilled to see the announcement and initiation of collaboration between CHIPS Alliance and RISC-V International on the OmniXtend Cache Coherency protocol. We have…
The Cybersecurity Pincushion and a Myriad of Tiny Threat Points“Large organizations are using over 130 tools on average. This is just massive!” - Matt Chiodi, CSO, Palo Alto Networks’ public cloud A new Cloud…
Check out the new RISC-V Careers page and RISC-V Mentorship program!We are excited to announce the new RISC-V Careers page and RISC-V Mentorship program! As the RISC-V ecosystem and community grow, we’re bringing together those…
FOSSi Fever 20202020 was a year with a lot of bad news and so it feels slightly strange to cheerfully write about a very specific topic in…
RISC-V Security Forum 2021 – Schedule Announced!The RISC-V Forums, hosted by RISC-V International, are short-form, single-topic, deep-dive virtual events. This is the spirit of RISC-V events - providing technical content to…
Growing an Open and Inclusive CommunityCollaboration underpins everything we do in the RISC-V community. That’s why we encourage everyone to join us and participate, and why we are working hard…
RISC-V Execution Stages | Maven SiliconThis video explains the execution stages of a RISC-V processor and how it executes all the instructions. Follow this RISC-V video blog series to obtain…
RISC-V Star Rising from the East – Introducing StarFiveWith the recent announcement of BeagleVTM, reported by premium technology media Ars Technica, Tom’s Hardware, CNX Software, as well as many others, a new name…
RISC-V growth and successes in technology and industry : embedded world 2021RISC-V International has more than 1,000 members across over 50 countries who are working in hardware, software, services, and various industries for a strong and…
OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IPThe RISC-V ISA (Instruction Set Architecture) permits a range of possibilities for processor implementation with a modular approach for standard and custom extensions. In addition,…
RISC-V Becoming Less Risky with the Right VerificationRISC-V continues to make headlines across the electronic design industry. You may have seen the recent news that the OpenHW Group is delivering their first…