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Jesse Taube Gets Linux Up and Running on the Raspberry Pi RP2350’s Hazard3 RISC-V Cores
RISC-V International N-Trace TG Milestone
Resiltech To Develop Test Libraries for Andes ASIL-D RISC-V Processor IP
Exploring the Amazing RISC-V Summit China 2024Resiltech and Andes Technology Announce Collaboration to Deliver Advanced STL Solutions for Andes Automotive-Grade RISC-V Processor IP
RISC-V World Tour; Munich, Hangzhou, Santa Clara…SEALSQ Testing Its QS7001 RISC V Quantum-Resistant PlatformC28 PQShield and SiFive Collaborate to Advance Post-Quantum Cryptography in RISC-V
Introducing the Newly Elected RISC-V Board of Directors Officers and Members
RISC-V SoC Design Workshop by Maven Silicon in Malaysia & Singapore
DeepComputing Opens Pre-Orders for the SpacemIT K1 RISC-V-Powered DC-ROMA RISC-V Pad II Tablet
Geniatech actively lays out RISC-V ecosystem to accelerate industrial IoT development
Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT project
Opening Up New Design Possibilities with OmniXtend
The Cybersecurity Pincushion and a Myriad of Tiny Threat Points
Check out the new RISC-V Careers page and RISC-V Mentorship program!
FOSSi Fever 2020
RISC-V Security Forum 2021 – Schedule Announced!
Growing an Open and Inclusive Community
RISC-V Execution Stages | Maven Silicon
RISC-V Star Rising from the East – Introducing StarFive
RISC-V growth and successes in technology and industry : embedded world 2021
OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IP
RISC-V Becoming Less Risky with the Right Verification
Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT projectOpening Up New Design Possibilities with OmniXtendThe Cybersecurity Pincushion and a Myriad of Tiny Threat PointsCheck out the new RISC-V Careers page and RISC-V Mentorship program!FOSSi Fever 2020RISC-V Security Forum 2021 – Schedule Announced!Growing an Open and Inclusive CommunityRISC-V Execution Stages | Maven SiliconRISC-V Star Rising from the East – Introducing StarFiveRISC-V growth and successes in technology and industry : embedded world 2021OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IPRISC-V Becoming Less Risky with the Right Verification
A RISC-V World First Independently Developed RISC-V Mainboard for a Framework Laptop from DeepComputing[VIDEO] RISC-V Con 2024: “Leveraging RISC-V for hardware software co-design of low power AI accelerators”[VIDEO] Banana Pi BPI-F3: Octa Core RISC-V SBC Running Bianbu OS
World’s first RISC-V Laptop gets a MASSIVE upgrade and equips with Ubuntu
[VIDEO] OpenHW Group CORE-V RISC-V open-source cores with CEO Florian ‘Flo’ Wohlrab at Computex 2024 Update
Lauterbach presents leading debug solutions at the RISC-V Summit in MunichWorld’s first RISC-V Laptop gets a MASSIVE upgrade and equips with Ubuntu
Axiomise Heads to RISC-V Summit Europe June 25-27 in Munich
Codasip introduces best-in-class RISC-V core for power-efficient applications
[VIDEO] ANDES RISC-V CON Silicon Valley 2024Arteris Selected by Esperanto Technologies to Integrate RISC-V Processors for High-Performance AI and Machine Learning Solutions[VIDEO] Progress in Standardizing Cryptography Extensions for RISC-V Processors
Jesse Taube Gets Linux Up and Running on the Raspberry Pi RP2350’s Hazard3 RISC-V CoresDeveloper Jesse Taube has become the first to successfully boot a minimal Linux distribution on the Raspberry Pi Pico 2's RP2350 microcontroller — taking advantage…
RISC-V International N-Trace TG MilestoneThe market is experiencing a major shift to the RISC-V ISA and MIPS is helping to fuel this transition with high performance RISC-V cores, including…
Resiltech To Develop Test Libraries for Andes ASIL-D RISC-V Processor IPAndes Technology in Taiwan has confirmed details of its deal with Italian software provider Resiltech for Software Test Libraries (STL) for automotive-grade RISC-V processor IP.…
Exploring the Amazing RISC-V Summit China 2024By: The RISC-V Summit China Team The 4th RISC-V Summit China 2024 was successfully held in Hangzhou from August 21st to 23rd. This summit brought…
Resiltech and Andes Technology Announce Collaboration to Deliver Advanced STL Solutions for Andes Automotive-Grade RISC-V Processor IPPontedera, Italy and Hsinchu, Taiwan – Aug 29th, 2024 – Resiltech, a renowned provider of comprehensive security and safety solutions and services, and Andes Technology, a leading supplier…
RISC-V World Tour; Munich, Hangzhou, Santa Clara…Ian Ferguson from SiFive attended the RISC-V event in Hangzhou, China, in August 2024. Explore his insights on the event's impressive scale, vibrant atmosphere, and…
SEALSQ Testing Its QS7001 RISC V Quantum-Resistant PlatformSEALSQ Testing its QS7001 RISC V Quantum-Resistant Platform I the Next Generation WISeSat Satellites; Prototype to Launch in November 2024 Geneva, Switzerland, Aug. 28,…
C28 PQShield and SiFive Collaborate to Advance Post-Quantum Cryptography in RISC-VLONDON and SANTA CLARA, Calif., Aug. 28, 2024 /PRNewswire/ -- PQShield, a leading quantum-safe cryptography provider, and RISC-V processing pioneer SiFive have partnered to deliver post-quantum cryptography on SiFive's Essential and Performance high-performance processor families,…
Introducing the Newly Elected RISC-V Board of Directors Officers and MembersThe RISC-V International Board of Directors and its officers are pivotal in guiding and leading the expansive RISC-V community. As members continue to make significant…
RISC-V SoC Design Workshop by Maven Silicon in Malaysia & SingaporeMaven Silicon’s Founder and CEO P R Sivakumar, and Principal Engineer Satish Putta are delivering a 3 days workshop on ‘RISC-V SoC Design’ in Malaysia…
DeepComputing Opens Pre-Orders for the SpacemIT K1 RISC-V-Powered DC-ROMA RISC-V Pad II TabletRISC-V specialist DeepComputing has unveiled a new portable computing gadget, powered by the SpacemIT K1 system-on-chip: the DC-ROMA RISC-V Pad II tablet computer. "DeepComputing is…
Geniatech actively lays out RISC-V ecosystem to accelerate industrial IoT developmentRecently, one of the world’s three major RISC-V professional exhibitions, the largest annual RISC-V event – 2024 RISC-V China Summit was held in Hangzhou, Zhe…
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Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT projectThe EU-funded Very Efficient Deep Learning in IoT (VEDLIoT) project is underway. Launched at the end of 2020, it aims to build a next-generation IoT…
Opening Up New Design Possibilities with OmniXtendI am thrilled to see the announcement and initiation of collaboration between CHIPS Alliance and RISC-V International on the OmniXtend Cache Coherency protocol. We have…
The Cybersecurity Pincushion and a Myriad of Tiny Threat Points“Large organizations are using over 130 tools on average. This is just massive!” - Matt Chiodi, CSO, Palo Alto Networks’ public cloud A new Cloud…
Check out the new RISC-V Careers page and RISC-V Mentorship program!We are excited to announce the new RISC-V Careers page and RISC-V Mentorship program! As the RISC-V ecosystem and community grow, we’re bringing together those…
FOSSi Fever 20202020 was a year with a lot of bad news and so it feels slightly strange to cheerfully write about a very specific topic in…
RISC-V Security Forum 2021 – Schedule Announced!The RISC-V Forums, hosted by RISC-V International, are short-form, single-topic, deep-dive virtual events. This is the spirit of RISC-V events - providing technical content to…
Growing an Open and Inclusive CommunityCollaboration underpins everything we do in the RISC-V community. That’s why we encourage everyone to join us and participate, and why we are working hard…
RISC-V Execution Stages | Maven SiliconThis video explains the execution stages of a RISC-V processor and how it executes all the instructions. Follow this RISC-V video blog series to obtain…
RISC-V Star Rising from the East – Introducing StarFiveWith the recent announcement of BeagleVTM, reported by premium technology media Ars Technica, Tom’s Hardware, CNX Software, as well as many others, a new name…
RISC-V growth and successes in technology and industry : embedded world 2021RISC-V International has more than 1,000 members across over 50 countries who are working in hardware, software, services, and various industries for a strong and…
OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IPThe RISC-V ISA (Instruction Set Architecture) permits a range of possibilities for processor implementation with a modular approach for standard and custom extensions. In addition,…
RISC-V Becoming Less Risky with the Right VerificationRISC-V continues to make headlines across the electronic design industry. You may have seen the recent news that the OpenHW Group is delivering their first…
No recent posts listed
Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT projectThe EU-funded Very Efficient Deep Learning in IoT (VEDLIoT) project is underway. Launched at the end of 2020, it aims to build a next-generation IoT…
Opening Up New Design Possibilities with OmniXtendI am thrilled to see the announcement and initiation of collaboration between CHIPS Alliance and RISC-V International on the OmniXtend Cache Coherency protocol. We have…
The Cybersecurity Pincushion and a Myriad of Tiny Threat Points“Large organizations are using over 130 tools on average. This is just massive!” - Matt Chiodi, CSO, Palo Alto Networks’ public cloud A new Cloud…
Check out the new RISC-V Careers page and RISC-V Mentorship program!We are excited to announce the new RISC-V Careers page and RISC-V Mentorship program! As the RISC-V ecosystem and community grow, we’re bringing together those…
FOSSi Fever 20202020 was a year with a lot of bad news and so it feels slightly strange to cheerfully write about a very specific topic in…
RISC-V Security Forum 2021 – Schedule Announced!The RISC-V Forums, hosted by RISC-V International, are short-form, single-topic, deep-dive virtual events. This is the spirit of RISC-V events - providing technical content to…
Growing an Open and Inclusive CommunityCollaboration underpins everything we do in the RISC-V community. That’s why we encourage everyone to join us and participate, and why we are working hard…
RISC-V Execution Stages | Maven SiliconThis video explains the execution stages of a RISC-V processor and how it executes all the instructions. Follow this RISC-V video blog series to obtain…
RISC-V Star Rising from the East – Introducing StarFiveWith the recent announcement of BeagleVTM, reported by premium technology media Ars Technica, Tom’s Hardware, CNX Software, as well as many others, a new name…
RISC-V growth and successes in technology and industry : embedded world 2021RISC-V International has more than 1,000 members across over 50 countries who are working in hardware, software, services, and various industries for a strong and…
OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IPThe RISC-V ISA (Instruction Set Architecture) permits a range of possibilities for processor implementation with a modular approach for standard and custom extensions. In addition,…
RISC-V Becoming Less Risky with the Right VerificationRISC-V continues to make headlines across the electronic design industry. You may have seen the recent news that the OpenHW Group is delivering their first…
A RISC-V World First Independently Developed RISC-V Mainboard for a Framework Laptop from DeepComputingToday, RISC-V pioneer DeepComputing announced that their first RISC-V Mainboard, compatible with the Framework Laptop 13, is about to be released. Sporting a RISC-V StarFive…
[VIDEO] RISC-V Con 2024: “Leveraging RISC-V for hardware software co-design of low power AI accelerators”Alexander Conklin, Head of Hardware Engineering, Rain AI The compute intensive demands of AI workloads have given rise to a new era in accelerator design.…
[VIDEO] Banana Pi BPI-F3: Octa Core RISC-V SBC Running Bianbu OSRISC-V Banana Pi BPI-F3 development board review and specifications, including demonstrations running Bianbu OS from SpaceMIT (who also developed the K1 RISC-V SoC on which…
World’s first RISC-V Laptop gets a MASSIVE upgrade and equips with UbuntuDeepComputing partners with Canonical to unveil a huge boost to the DC-ROMA RISC-V Laptop family The DC-ROMA RISC-V Laptop II is the world’s first RISC-V…
[VIDEO] OpenHW Group CORE-V RISC-V open-source cores with CEO Florian ‘Flo’ Wohlrab at Computex 2024 UpdateFlorian "Flo" Wohlrab, CEO of OpenHW Group, leads a Canadian-based nonprofit that operates globally, focusing on open-source hardware. The organization specializes in creating industrial-grade, fully…
Lauterbach presents leading debug solutions at the RISC-V Summit in MunichHoehenkirchen, Germany - June 13, 2024 - Under the headline "RISC-V Debugging made Easy", Lauterbach, the leading supplier of RISC-V debug and trace tools, will…
World’s first RISC-V Laptop gets a MASSIVE upgrade and equips with UbuntuDeepComputing partners with Canonical to unveil a huge boost to the DC-ROMA RISC-V Laptop family The DC-ROMA RISC-V Laptop II is the world’s first RISC-V…
Axiomise Heads to RISC-V Summit Europe June 25-27 in MunichLONDON, June 13, 2024 (GLOBE NEWSWIRE) -- Axiomise, a company noted for enabling formal verification adoption, is headed to the RISC-V Summit Europe to demonstrate…
Codasip introduces best-in-class RISC-V core for power-efficient applicationsMunich, Germany, June 4, 2024 – Codasip, the leader in RISC-V Custom Compute, has introduced a new low-power embedded processor core, and the next generation…
[VIDEO] ANDES RISC-V CON Silicon Valley 2024ANDES had their RISC-V Con in Silicon Valley on June 11th. No worries if you weren't able to make it, watch the full conference to…
Arteris Selected by Esperanto Technologies to Integrate RISC-V Processors for High-Performance AI and Machine Learning SolutionsCAMPBELL, Calif. – June 11, 2024 – Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced that…
[VIDEO] Progress in Standardizing Cryptography Extensions for RISC-V ProcessorsThis panel will discuss the state of standardized cryptographic instruction set extensions for RISC-V processors. Lightweight instructions for scalar CPUs, high-performance instructions for vector CPUs,…