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reCamera modular AI camera features SG2002 RISC-V AI SoC, supports interchangeable image sensors and baseboards
RISC-V Summit North America T-Shirt Design Contest—And the Winner Is…!
XiangShan High-Performance RISC-V Processors at Hot Chips 2024Tenstorrent’s Blackhole Chips Boast 768 RISC-V Cores and Almost as Many FLOPS
CHERIoT: A Study in CHERI
Join the ranks of RISC-V Advocates!
Infineon Harnesses the Power of RISC-V for Next-Generation Automotive MCU Innovation
Featured Work: Microarchitecture Security: The Spectre AffairNew RISC-V Innovations Lead AI to Open Standard
[VIDEO] Join us for This Year’s RISC-V Summit
Unlocking the Potential of Your RISC-V Laptop: The DC-ROMA Laptop IISEALSQ introduces new RISC-V secure hardware platform for IoT security
High-throughput open source PCIe on Xilinx VU19P-based ASIC prototyping platform
Hardware Description Language Chisel & Diplomacy Deeper dive
Where to start with RISC-VOverview of Diplomacy for writing effective hardware design language Chisel (Japanese)
RISC-V CPU Performance | Maven Silicon
Let’s Make RISC-V Connected Systems Synonymous with Security
RISC-V Microarchitecture for Kids??!! | Steve Hoover, Redwood EDA
What is Processor Core Complexity?
What is Needed to Support an Operating System?
Understanding the Performance of Processor IP Cores
RPC DRAM support in open source DRAM controller
13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core
High-throughput open source PCIe on Xilinx VU19P-based ASIC prototyping platformHardware Description Language Chisel & Diplomacy Deeper diveWhere to start with RISC-VOverview of Diplomacy for writing effective hardware design language Chisel (Japanese)RISC-V CPU Performance | Maven SiliconLet’s Make RISC-V Connected Systems Synonymous with SecurityRISC-V Microarchitecture for Kids??!! | Steve Hoover, Redwood EDAWhat is Processor Core Complexity?What is Needed to Support an Operating System?Understanding the Performance of Processor IP CoresRPC DRAM support in open source DRAM controller13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core
[VIDEO] Progress in Standardizing Cryptography Extensions for RISC-V ProcessorsFirst 32-bit low-power MCU with in-house RISC-V CPU coreSpacemiT Muse Pi is a single-board PC with SpacemiT M1 8-core RISC-V processor
Andes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose HotelGetting started with RISC-V! | Soham Kulkarni | MumbaiFOSS 2024Navigating the RISC-V landscape: unveiling the Embeetle IDECalligo Technologies Unveils Revolutionary World’s First Posit-enabled RISC-V CPU for General Purpose ComputingRain AI Unveils Andes Technology as Its RISC-V Partner
Andes Technology announces new SoC and development boardAndes Technology Announced the QiLai SoC and the Voyager Development BoardBuilding a DIY 256-Core RISC-V computer[VIDEO] The Magic of RISC-V Vector Processing
reCamera modular AI camera features SG2002 RISC-V AI SoC, supports interchangeable image sensors and baseboardsSeeed Studio’s reCamera AI camera is a modular RISC-V smart camera system for edge AI applications based on SOPHGO SG2002 SoC. The camera is made…
RISC-V Summit North America T-Shirt Design Contest—And the Winner Is…!In a nod to the creativity and innovation of the RISC-V community, this year RISC-V International hosted the first RISC-V Summit North America T-shirt design…
XiangShan High-Performance RISC-V Processors at Hot Chips 2024XiangShan is a RISC-V CPU project out of China, and now hosted on Github. This is a high-performance CPU design, instead of lower performance designs…
Tenstorrent’s Blackhole Chips Boast 768 RISC-V Cores and Almost as Many FLOPSHot Chips RISC-V champion Tenstorrent offered the closest look yet at its upcoming Blackhole AI accelerators at Hot Chips this week, which they claim can outperform…
CHERIoT: A Study in CHERIAuthors: Tony Chen, Nathaniel Wesley Filardo, Kunyan Liu, Robert Norton-Wright, Yucong Tao CHERIoT (Capability Hardware Extension to RISC-V for Internet of Things) is a 32-bit…
Join the ranks of RISC-V Advocates!We are looking for RISC-V enthusiasts from around the world to become key players in supporting RISC-V progress through global promotion and engagement. As an…
Infineon Harnesses the Power of RISC-V for Next-Generation Automotive MCU InnovationBy: Thomas Böhm - SVP Automotive Microcontroller, Infineon One of the megatrends in the automotive industry is the Software Defined Vehicle (SDV), where major innovations…
Featured Work: Microarchitecture Security: The Spectre AffairAuthor: Ronan Lashermes, Hardware Security Research Engineer at Inria. Results from a joint work with Hery Andrianatrehina, Joseph Paturel, Simon Rokicki and Thomas Rubiano at…
New RISC-V Innovations Lead AI to Open StandardIf the growing number of new RISC-V announcements aren’t enough proof of the license-free protocol’s momentum, there is a mountain of analyst predictions, trend research,…
[VIDEO] Join us for This Year’s RISC-V SummitFrom the IoT edge to the depths of space, RISC-V enables groundbreaking innovations. Join us at the RISC-V Summit 2024, October 22–23, at the Santa…
Unlocking the Potential of Your RISC-V Laptop: The DC-ROMA Laptop IIThe DC-ROMA Laptop II has undergone comprehensive upgrades in both hardware and software, offering enhanced computing power and energy efficiency, as well as extensive system…
SEALSQ introduces new RISC-V secure hardware platform for IoT securityWith the need for more robust, quantum-resilient security the company’s new platform represents a significant advancement in securing critical data and infrastructure against the threats…
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High-throughput open source PCIe on Xilinx VU19P-based ASIC prototyping platformOriginally published by Antmicro In the daily work at Antmicro, they use FPGAs primarily for their flexibility and parallel data processing capabilities that make…
Hardware Description Language Chisel & Diplomacy Deeper diveAre you using Chisel? A hardware building language based on Scala. Not a high-level synthesis language. SiFive's RISC-V IP use Chisel Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom…
Where to start with RISC-VOriginally posted on Medium How to get started, where to contribute, and what to do next RISC-V made the news recently when BeagleBoard.org revealed the…
Overview of Diplomacy for writing effective hardware design language Chisel (Japanese)ハードウェア記述言語Chiselをもっともっと活用するためのDiplomacy概説 発表者：msyksphinz (FPGA開発日記著者) @msyksphinz_dev https://msyksphinz.hatenablog.com Chisel使ってますか？ Scalaをベースとしたハードウェア構築言語. 高位合成言語ではない SiFiveのRISC-V IPで採用されている Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom Chiselの基礎 : 「Chiselを始めたい人に読んで欲しい本」 https://nextpublishing.jp/book/12162.html ChiselがVerilogを生成するまで ChiselはScalaのDSLなので、Chisel CompilerはScalaで記述してある Chisel CompilerはFIR (Flexible Interpretation Representation)と呼ばれる中間言語を生成する…
RISC-V CPU Performance | Maven SiliconThis video explains how Maven Silicon measures the CPU performance and how we try to improve the processor performance by improving its clock frequency and…
Let’s Make RISC-V Connected Systems Synonymous with SecurityThis blog was submitted by Silex Insight. If you are designing systems based on a RISC-V architecture, for example to run highly connected applications,…
RISC-V Microarchitecture for Kids??!! | Steve Hoover, Redwood EDALast month I had the great pleasure of sharing a blog post about Nicholas Sharkey, an amazing 13 year-old who participated with graduate students and…
What is Processor Core Complexity?This blog was originally published on the Codasip blog. The more complex a processor core, the larger the area and power consumption. But increasing…
What is Needed to Support an Operating System?This blog was originally published on the Codasip blog. For each embedded product, software developers need to consider whether they need an operating system;…
Understanding the Performance of Processor IP CoresThis blog was originally published on the Codasip blog. Looking at any processor IP, you will find that their vendors emphasise PPA (performance, power…
RPC DRAM support in open source DRAM controllerOriginal content published October 28, 2020 on the Antmicro blog. The Internet of Things is one of the areas that is hugely benefiting from miniaturization…
13-Year-Old, Nicholas Sharkey, Creates a RISC-V CoreOne of my great pleasures operating my EDA startup, Redwood EDA, is working with enthusiastic college students and open-source developers and seeing how our technology…
No recent posts listed
High-throughput open source PCIe on Xilinx VU19P-based ASIC prototyping platformOriginally published by Antmicro In the daily work at Antmicro, they use FPGAs primarily for their flexibility and parallel data processing capabilities that make…
Hardware Description Language Chisel & Diplomacy Deeper diveAre you using Chisel? A hardware building language based on Scala. Not a high-level synthesis language. SiFive's RISC-V IP use Chisel Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom…
Where to start with RISC-VOriginally posted on Medium How to get started, where to contribute, and what to do next RISC-V made the news recently when BeagleBoard.org revealed the…
Overview of Diplomacy for writing effective hardware design language Chisel (Japanese)ハードウェア記述言語Chiselをもっともっと活用するためのDiplomacy概説 発表者：msyksphinz (FPGA開発日記著者) @msyksphinz_dev https://msyksphinz.hatenablog.com Chisel使ってますか？ Scalaをベースとしたハードウェア構築言語. 高位合成言語ではない SiFiveのRISC-V IPで採用されている Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom Chiselの基礎 : 「Chiselを始めたい人に読んで欲しい本」 https://nextpublishing.jp/book/12162.html ChiselがVerilogを生成するまで ChiselはScalaのDSLなので、Chisel CompilerはScalaで記述してある Chisel CompilerはFIR (Flexible Interpretation Representation)と呼ばれる中間言語を生成する…
RISC-V CPU Performance | Maven SiliconThis video explains how Maven Silicon measures the CPU performance and how we try to improve the processor performance by improving its clock frequency and…
Let’s Make RISC-V Connected Systems Synonymous with SecurityThis blog was submitted by Silex Insight. If you are designing systems based on a RISC-V architecture, for example to run highly connected applications,…
RISC-V Microarchitecture for Kids??!! | Steve Hoover, Redwood EDALast month I had the great pleasure of sharing a blog post about Nicholas Sharkey, an amazing 13 year-old who participated with graduate students and…
What is Processor Core Complexity?This blog was originally published on the Codasip blog. The more complex a processor core, the larger the area and power consumption. But increasing…
What is Needed to Support an Operating System?This blog was originally published on the Codasip blog. For each embedded product, software developers need to consider whether they need an operating system;…
Understanding the Performance of Processor IP CoresThis blog was originally published on the Codasip blog. Looking at any processor IP, you will find that their vendors emphasise PPA (performance, power…
RPC DRAM support in open source DRAM controllerOriginal content published October 28, 2020 on the Antmicro blog. The Internet of Things is one of the areas that is hugely benefiting from miniaturization…
13-Year-Old, Nicholas Sharkey, Creates a RISC-V CoreOne of my great pleasures operating my EDA startup, Redwood EDA, is working with enthusiastic college students and open-source developers and seeing how our technology…
[VIDEO] Progress in Standardizing Cryptography Extensions for RISC-V ProcessorsThis panel will discuss the state of standardized cryptographic instruction set extensions for RISC-V processors. Lightweight instructions for scalar CPUs, high-performance instructions for vector CPUs,…
First 32-bit low-power MCU with in-house RISC-V CPU coreMouser now stocks the R9A02G021 low-power MCUs from Renesas Electronics. Empowering engineers with a multipurpose platform for creating power-efficient, cost-effective applications using an open-source ISA,…
SpacemiT Muse Pi is a single-board PC with SpacemiT M1 8-core RISC-V processorEarlier this year Chinese chip maker SpacemiT announced plans to launch several new products powered by the company’s RISC-V processors, including the SpacemiT Muse Book…
Andes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose HotelSan Jose, CA — Jun 6, 2024 — Andes Technology (TWSE: 6533), the leading vendor in high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding…
Getting started with RISC-V! | Soham Kulkarni | MumbaiFOSS 2024Soham shares his knowledge about RISC-V at the MumbaiFOSS 2024 Conference! Watch the full video here.
Navigating the RISC-V landscape: unveiling the Embeetle IDEEmbeetle was founded by three engineers with unique insights into embedded software IDEs. The Embeetle team is committed to building a healthy MCU ecosystem, offering…
Calligo Technologies Unveils Revolutionary World’s First Posit-enabled RISC-V CPU for General Purpose ComputingBENGALURU, India, June 3, 2024 /PRNewswire/ -- Calligo Technologies Pvt Ltd, a pioneering tech firm based in Bengaluru, India, proudly announces the world's first 8-core Posit-enabled…
Rain AI Unveils Andes Technology as Its RISC-V PartnerSan Francisco, CA , June 03, 2024 (GLOBE NEWSWIRE) -- Rain AI Licenses Andes AX45MPV and Taps Andes Custom Computing BU to Accelerate Its Launch…
Andes Technology announces new SoC and development boardAndes Technology, a supplier of 32/64-bit RISC-V processor cores, has unveiled the QiLai SoC and the Voyager development board to help accelerate the development and…
Andes Technology Announced the QiLai SoC and the Voyager Development BoardMay 30, 2024 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding…
Building a DIY 256-Core RISC-V computerIf you’re interested in building your very own 256-Core RISC-V supercomputer, you might find this project video intriguing. It details the ambitious method of creating…
[VIDEO] The Magic of RISC-V Vector ProcessingThe 1.0 RISC-V Vector Specification is now Ratified, and the first pieces of silicon using the new spec are starting to hit the shelves. I…