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BRAZIL AND EUROPE SIGN INNOVATIVE PROJECT WITH RISC-V TECHNOLOGY FOR HPC
MIPS Expands Global Footprint with New Design Center and Talent for Systems Architects and AI ComputeStarFive’s RISC-V Based JH-7110 Intelligent Vision Processing Platform Adopted VeriSilicon’s Display Processor IP
A custom RISC-V vector instruction to accelerate structured-sparse matrix multiplications
Advanced RISC-V Training Course | Maven Silicon – RISC-V Global Training Partner
RISC-V International Newsletter – March 2024
Introducing the RISC-V Enterprise Software Ecosystem DashboardGlobal and China Automotive RISC-V Chip Industry Research Report 2024: Customized Chips May Become the Future Trend, and RISC-V will Challenge ARMSecuring software execution with CHERI on a Codasip A730 RISC-V core
SiFive Upgrades Automotive Security for the RISC-V Ecosystem with New ISO/SAE 21434 CertificationCanaan’s RISC-V based edge AIoT SoC adopted VeriSilicon’s ISP and GPU IPs
S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V ProcessorGoogle will release Android RISC-V emulators to test apps in 2024Hyperion Core Joins RISC-V International as a Strategic MemberAndroid and RISC-V: What you need to know to be ready
CHIPS Alliance Technology UpdateTop 5 Facts about RISC-V – Tom’s Top Five
On the EVE of the RISC-V Summit North America
Ashling and InCore announce Ashling’s RiscFree™ C/C++ SDK support for InCore’s RISC-V-based Azurite Cores.
Microchip Showcases Expanded RISC-V-Based Solutions, Partnerships and System Design Tools at 2023 RISC-V SummitHarnessing the RISC-V Wave: The Future is Now
First fully coherent RISC-V Tensor unit for AI chip designSemidynamics launches first fully-coherent RISC-V Tensor unit to supercharge AI applications
BRAZIL AND EUROPE SIGN INNOVATIVE PROJECT WITH RISC-V TECHNOLOGY FOR HPCAn international collaboration will enable Brazil to develop RISC-V technologies to accelerate research and development in the areas of semiconductors and supercomputing in the country.…
MIPS Expands Global Footprint with New Design Center and Talent for Systems Architects and AI ComputeSAN JOSE, Calif.--(BUSINESS WIRE)--MIPS, a leading developer of efficient and configurable compute cores, today announced the company’s global expansion with the launch of a new…
StarFive’s RISC-V Based JH-7110 Intelligent Vision Processing Platform Adopted VeriSilicon’s Display Processor IPSHANGHAI--(BUSINESS WIRE)--VeriSilicon (688521.SH) today announced the successful integration of its Display Processor IP DC8200 into StarFive’s JH-7110 RISC-V mass production SoC. With high performance, low…
A custom RISC-V vector instruction to accelerate structured-sparse matrix multiplicationsA novel AI-acceleration paper presents a method to optimize sparse matrix multiplication for machine learning models, particularly focusing on structured sparsity. Structured sparsity involves a predefined pattern…
Advanced RISC-V Training Course | Maven Silicon – RISC-V Global Training PartnerBy Sivakumar P R In this video, our Founder and CEO, Mr. P R Sivakumar, explains how he has authored the new RISC-V training course…
RISC-V International Newsletter – March 2024Message from RISC-V International 2024 is now well underway and we have some exciting new developments from our members worldwide! RISC-V is truly a global…
Introducing the RISC-V Enterprise Software Ecosystem DashboardAuthor: Isaac Chute, Director of Software Ecosystem, RISC-V International Historically there have been many iterations of compute platforms, such as Alpha, Vax, Solaris, PA-RISC, x86,…
Global and China Automotive RISC-V Chip Industry Research Report 2024: Customized Chips May Become the Future Trend, and RISC-V will Challenge ARMDUBLIN, March 14, 2024 /PRNewswire/ -- The "Automotive RISC-V Chip Industry Research Report, 2024" report has been added to ResearchAndMarkets.com's offering. Read the full release.
Securing software execution with CHERI on a Codasip A730 RISC-V coreAuthor: Roddy Urquhart, Sr Technical Marketing Director, Codasip Introducing CHERI With cyber-attacks on systems growing in frequency and sophistication it is essential to improve the…
SiFive Upgrades Automotive Security for the RISC-V Ecosystem with New ISO/SAE 21434 CertificationSecuring your vehicle used to mean remembering to lock your doors at night and hiding your belongings under the seat when parked in public lots.…
Canaan’s RISC-V based edge AIoT SoC adopted VeriSilicon’s ISP and GPU IPsSHANGHAI--(BUSINESS WIRE)--VeriSilicon (688521.SH) today announced the integration of its Image Signal Processor (ISP) IP ISP8000, DeWarp Processor IP DW200, and 2.5D Graphics Processor Unit (GPU)…
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S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V ProcessorS2C announced that the Beijing Institute of Open Source Chip (BOSC) adopted its Prodigy S7-19P Logic System, a VU19P-based FPGA prototyping solution, in the development…
Google will release Android RISC-V emulators to test apps in 2024Earlier this month, Qualcomm announced it was working with Google on a RISC-V Wear OS chip. The Android team today provided an update on RISC-V adoption, including an…
Hyperion Core Joins RISC-V International as a Strategic MemberDüsseldorf, 30 October, 2023 – Hyperion Core Joins RISC-V International as a Strategic Member Hyperion Core, the company that brings affordable AI processing to the…
Android and RISC-V: What you need to know to be readyIn December of 2022, Google announced at the RISC-V Summit that they were accepting Android patches for RISC-V. On the Google Open Source Blog, Lars…
CHIPS Alliance Technology UpdateJoin us for the next Technology Update featuring informative, technical talks on open source hardware collaborative development. Hosted by Google in Sunnyvale, California, the event…
Top 5 Facts about RISC-V – Tom’s Top FiveRISC-V is an open-source instruction set architecture that can be used to develop custom processors. It's challenging not just Intel and AMD but Arm as…
On the EVE of the RISC-V Summit North AmericaThe ESD Alliance hosted an engrossing evening in the early days of RISC-V featuring two of its authors. At the time, RISC-V was a fledgling…
Ashling and InCore announce Ashling’s RiscFree™ C/C++ SDK support for InCore’s RISC-V-based Azurite Cores.October-17, 2023, Chennai, India and Limerick, Ireland. Fabless processor core IP provider InCore Semiconductors and embedded tools developer Ashling today announced support for the Azurite…
Microchip Showcases Expanded RISC-V-Based Solutions, Partnerships and System Design Tools at 2023 RISC-V SummitCHANDLER, Ariz., October 25, 2023, RISC-V Summit — Designers who create systems for the complex Intelligent Edge need flexible, high-performance hardware and system-software combinations that easily…
Harnessing the RISC-V Wave: The Future is NowRISC-V is inevitable - it became the mantra of RISC-V, and it's true. But before we see why that is, let’s step back and discuss…
First fully coherent RISC-V Tensor unit for AI chip designSemiDynamics in Spain has developed a RISC-V Tensor Unit for AI chip design based on its fully customisable 64bit cores. The RISC-V Tensor unit is…
Semidynamics launches first fully-coherent RISC-V Tensor unit to supercharge AI applicationsBarcelona, Spain – 24 October, 2023. Semidynamics has just announced a RISC-V Tensor Unit that is designed for ultra-fast AI solutions and is based on its…