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The Growing Momentum of RISC-V in Europe
YOLOX for Object Detection
SiFive’s WorldGuard Security Platform Now Available to the Entire RISC-V Ecosystem
Making the most of the 60th DAC
Polos CH32Vxx 32-bit RISC-V MCU boards starts at $1.99
Startups Help RISC-V Reshape Computer ArchitectureRISC-V Fast-Forwards, Breaks Ground for Auto Innovations
The industry’s first RISC-V IoT security chip, “Towngas Chip”, had sold over 1,000,000 pieces
THIS RISC-V CPU GAMES IN RUST FROM INSIDE THE GAME
DAC 2023: RISC-V is not in the future, it’s now
PODCAST: RISC-V International, Today and Tomorrow with Calista Redmond
Ashling announces RiscFree™ C/C++ SDK support for Lattice RISC-V MCU CPU Soft IP Cores
Implementation of RISCduino core using a Hierarchical Design Flow | Dinesh Annayya, OpenRoad
MIPS Rolls Out Its First RISC-V Processor Core – It’s a Big ‘Un | Steve Leibson, EE Journal
A chip design that changes everything: 10 Breakthrough Technologies 2023 | Sophia Chen, MIT Technology Review
RISC-V Hibernation Support / Suspend-To-Disk Nears The Linux Kernel | Michael Larabel, Phoronix
Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core | Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Marco Ottavi and Mauro OlivieriTCADer: A Tightly Coupled Accelerator Design framework for heterogeneous system with hardware/software co-design based on RISC-V | Wenqing Li, Tianyi Liu, Ziyuan Xiao HanQi, Weipu Zhu, Jian Wang
VisionFive 2: RISC-V Quad Core Low Cost SBC | Christopher Barnatt, Explaining Computers
Podcast EP135: Democratizing HPC & AI | Inspire Semiconductor, Semiwiki.com
Alexander Williams’ FiveForths Is a “Hand-Written” RISC-V Assembly Forth for Microcontrollers | Gareth Halfacree, Hackster.io
Week In Review: Design, Low Power | Marie C. Baca, Semiconductor Engineering
MangoPi MQ-PRO Review: RISC-V Raspberry Pi Zero Alternative? | Learn Embedded Systems
Google to Make RISC-V a Major Platform for Android | Robin Mitchell, Electropages
The Growing Momentum of RISC-V in EuropeBy: Kezia Leung The RISC-V Summit Europe brought together members of the RISC-V community from industry, government, research, and academia to explore how RISC-V is…
YOLOX for Object DetectionAuthor: Meng Chang This topic presents an example about how to deploy a YOLOX model on a RISC-V development board for object detection. The content…
SiFive’s WorldGuard Security Platform Now Available to the Entire RISC-V EcosystemData and codes are only as powerful as the security platform that protects them. Without a robust security model for isolated code execution and data…
Making the most of the 60th DACI just returned from a week in San Francisco where I attended the 60th Design Automation Conference. It was a typical week at DAC — cold weather in July,…
Polos CH32Vxx 32-bit RISC-V MCU boards starts at $1.99XPU Labs, a subsidiary of AnalogLamb, has designed three inexpensive “Polos” development boards based on WCH CH32VXX RISC-V microcontrollers with pricing starting at just $1.99. The…
Startups Help RISC-V Reshape Computer ArchitectureThe RISC-V instruction set architecture (ISA) is one of the most notable contenders to emerge in the ever-evolving realm of computer architecture. Because of its…
RISC-V Fast-Forwards, Breaks Ground for Auto InnovationsThe SiFive RISC-V Automotive CPU IP continues to advance to address and enable automotive applications like infotainment, connectivity and advanced driver-assistance systems. Yet without the…
The industry’s first RISC-V IoT security chip, “Towngas Chip”, had sold over 1,000,000 piecesJuly 17, 2023 -- Towngas Group officially announced that the sales of the first RISC-V IoT security chip "Towngas Chip" had exceeded 1 million pieces, which…
THIS RISC-V CPU GAMES IN RUST FROM INSIDE THE GAMEhas created something truly impressive — a working RISC-V CPU completely contained in a Terraria world. And then for added fun, he wrote the game of…
DAC 2023: RISC-V is not in the future, it’s nowAt this year’s Design Automation Conference (DAC), there was a panel discussion entitled, “Delivering on RISC V’s Promise to Give Designers Freedom to Innovate –…
PODCAST: RISC-V International, Today and Tomorrow with Calista RedmondDan is joined by Calista Redmond, CEO of RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including Vice President of IBM Z…
Ashling announces RiscFree™ C/C++ SDK support for Lattice RISC-V MCU CPU Soft IP CoresLimerick, Ireland – July 14, 2023 – Ashling today announced its RiscFree SDK has been added to the Lattice Semiconductor RISC-V ® MC CPU soft…
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Implementation of RISCduino core using a Hierarchical Design Flow | Dinesh Annayya, OpenRoadDinesh Annaya is an ardent Open-Source EDA enthusiast and an expert user of OpenROAD and OpenLane. He developed a baseline RISCduino SoC, a single, 32…
MIPS Rolls Out Its First RISC-V Processor Core – It’s a Big ‘Un | Steve Leibson, EE JournalEven though the company had telegraphed its big move, MIPS’s adoption of the RISC-V ISA for its future processor cores hit me like a ton…
A chip design that changes everything: 10 Breakthrough Technologies 2023 | Sophia Chen, MIT Technology ReviewComputer chip designs are expensive and hard to license. That’s all about to change thanks to the popular open standard known as RISC-V. Ever wonder…
RISC-V Hibernation Support / Suspend-To-Disk Nears The Linux Kernel | Michael Larabel, PhoronixWhile the open RISC-V processor architecture has proven to be highly successful, one of the features that it hasn't yet supported with the Linux kernel…
Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core | Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Marco Ottavi and Mauro OlivieriAbstract: Functional safety is a key requirement in several application domains in which microprocessors are an essential part. A number of redundancy techniques have been…
TCADer: A Tightly Coupled Accelerator Design framework for heterogeneous system with hardware/software co-design based on RISC-V | Wenqing Li, Tianyi Liu, Ziyuan Xiao HanQi, Weipu Zhu, Jian WangAbstract - Domain-specific architectures (DSAs) or hardware accelerators are typical innovations that are leading computer architecture into a new golden age. In a heterogeneous system,…
VisionFive 2: RISC-V Quad Core Low Cost SBC | Christopher Barnatt, Explaining ComputersStarFive VisionFive 2 RISC-V SBC review, including a demo of an engineering release of Debian, and of Python GPIO control. My previous “Explaining RISC-V” video…
Podcast EP135: Democratizing HPC & AI | Inspire Semiconductor, Semiwiki.comDan is joined by Doug Norton, VP of Business Development for Inspire Semiconductor, an Austin-based high performance computing chip design company. He is also the President of…
Alexander Williams’ FiveForths Is a “Hand-Written” RISC-V Assembly Forth for Microcontrollers | Gareth Halfacree, Hackster.ioWritten in RISC-V assembly, this tiny Forth port is open source and fully functional on the Longan Nano microcontroller. Developer Alexander Williams has written and…
Week In Review: Design, Low Power | Marie C. Baca, Semiconductor EngineeringTop Of The News Google announced it will support the RISC-V architecture with the Android open-source operating system. In a keynote at the RISC-V Summit, Lars Bergstrom, Google’s director of engineering for…
MangoPi MQ-PRO Review: RISC-V Raspberry Pi Zero Alternative? | Learn Embedded SystemsIn a time when Raspberry Pi’s are few and far between, alternative options such as the MangoPi MQ-PRO are increasingly interesting. In this review we…
Google to Make RISC-V a Major Platform for Android | Robin Mitchell, ElectropagesAs RISC-V continues to increase in popularity, many businesses are now turning to the processor architecture, including Google, which has just recently announced that RISC-V…