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The Incredible Growth of RISC-V in India
BeagleBoard.org Moves Along with its BeagleV-AheadBeagleV-Ahead is a single-board RISC-V computer that’s compatible with BeagleBone add-onsBeagleV-Ahead RISC-V computer from BeagleBoard.org available now under $150
Bluespec’s newest RISC-V chip adds customization capabilities for edge workloads
VIDEO: A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUsTowards a RISC-V Open Platform for Next-generation Automotive ECUsImperas details verification of automotive AI RISC-V vector processor IP
Open Source and CI-driven RTL Testing and Verification for Caliptra’s RISC-V VeeR Core
LicheePi 4A RISC-V SBC gets 16GB/128GB version, metal enclosure, 10.1-inch display, and more accessories
Upcoming low cost RISC-V breakout boards start at $1.99
Cadence and Imperas Support NSITEXE in the Development of Advanced RISC V Vector Processor IP for Automotive AI Applications
Google to Make RISC-V a Major Platform for Android | Robin Mitchell, Electropages
How Secure Are RISC-V Chips? | Jeff Goldman, Semiconductor Engineering
Grokking RISC-V Vector Processing | Erik Engheim, ITNext
Exploring the Benefits of RISC-V ISA for Posit Arithmetic at HiPEAC Conference | Federico – The AI Blog
News Espressif Reveals ESP32-P4: A High-Performance MCU with Numerous IO-Connectivity and Security Features | Espressif Systems
Ventana Introduces CES Audience to World’s Highest Performance RISC-V CPU, Veyron V1 | Ventana Micro SystemsA Bottom-Up Methodology for the Fast Assessment of CNN Mappings on Energy-Efficient Accelerators | Guillaume Devic, Gilles Sassatelli and Abdoulaye Gamatié
Ventana Introduces CES Audience to World’s Highest Performance RISC-V CPU, Veyron V1 | Ventana Micro Systems, Yahoo! Finance
RISC-V could become a first-class citizen for Android, Pixel 7a hands-on video leaked, and GeForce Now adds a RTX 4080 tier | Brad Linder, Liliputing
Breker Verification Systems Unveils Easy-To-Adopt Integrity FASTApps Targeting RISC-V Processor Core, SoC Verification Scenarios | Breker Verification Systems
Google wants RISC-V to be a “tier-1” Android architecture | Ron Amadeo, Ars Technica
RISC-V Summit 2022: All Your CPUs Belong to Us | Kevin Krewell, EE Times
The Incredible Growth of RISC-V in IndiaRISC-V is being adopted around the world as the silicon industry looks to the open RISC-V instruction set architecture (ISA) to offer a new level…
BeagleBoard.org Moves Along with its BeagleV-AheadBeagleBoard.org is now delivery its BeagleV-Ahead single board computer (SBC) based on the TH1520, a quad core 64-bit RISC-V SoC from T-Head. The SBC utilizes the open-source…
BeagleV-Ahead is a single-board RISC-V computer that’s compatible with BeagleBone add-onsBeagleBoard has launched a new single-board computer called the BeagleV-Ahead. It’s the same shape as the company’s BeagleBone Black and it’s compatible with some accessories designed for that…
BeagleV-Ahead RISC-V computer from BeagleBoard.org available now under $150BeagleBoard.org®, a leading developer of open-source hardware platforms, is thrilled to announce the highly anticipated launch of BeagleV® Ahead, an innovative single board computer (SBC) based…
Bluespec’s newest RISC-V chip adds customization capabilities for edge workloadsBluespec, a RISC-V tools and silicon IP provider, has introduced a processor design based on the open standard RISC-V instruction set architecture that will allow…
VIDEO: A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUsA Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs Lukas Gerlach (CISPA Helmholtz Center for Information Security), Daniel Weber (CISPA Helmholtz Center for Information Security),…
Towards a RISC-V Open Platform for Next-generation Automotive ECUsAbstract—The complexity of automotive systems is increasing quickly due to the integration of novel functionalities such as assisted or autonomous driving. However, increasing complexity poses…
Imperas details verification of automotive AI RISC-V vector processor IPImperas Software in the UK and Cadence Design Systems have detailed the verificaiton flow for NSITEXE developing an automotive AI RISC-V processor core. The two…
Open Source and CI-driven RTL Testing and Verification for Caliptra’s RISC-V VeeR CoreAs part of CHIPS Alliance’s mission to enable a software-driven approach to silicon, working with Google and other CHIPS members, Antmicro has been developing and improving…
LicheePi 4A RISC-V SBC gets 16GB/128GB version, metal enclosure, 10.1-inch display, and more accessoriesLicheePi 4A quad-core RISC-V SBC is now available with 16GB RAM and 128GB eMMC flash, and Sipeed has also introduced various accessories such as a…
Upcoming low cost RISC-V breakout boards start at $1.99AnalogLamb is set to release three affordable RISC-V breakout boards. These boards are based on the CHV32 Series microcontrollers offering support for standard interfaces such…
Cadence and Imperas Support NSITEXE in the Development of Advanced RISC V Vector Processor IP for Automotive AI ApplicationsOxford, United Kingdom, July 10th, 2023 — Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Cadence Design Systems, Inc. (Nasdaq: CDNS) has collaborated…
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Google to Make RISC-V a Major Platform for Android | Robin Mitchell, ElectropagesAs RISC-V continues to increase in popularity, many businesses are now turning to the processor architecture, including Google, which has just recently announced that RISC-V…
How Secure Are RISC-V Chips? | Jeff Goldman, Semiconductor EngineeringOpen source by itself doesn’t guarantee security. It still comes down to the fundamentals of design. When the Meltdown and Spectre vulnerabilities were first uncovered…
Grokking RISC-V Vector Processing | Erik Engheim, ITNextA friendly introduction to the core concepts in the RISC-V “V” Vector Extension, version 1.0. While the basic idea of vector processing is simple, the…
Exploring the Benefits of RISC-V ISA for Posit Arithmetic at HiPEAC Conference | Federico – The AI BlogI am excited to announce that I will be giving a talk at the HiPEAC conference on the RISC-V ISA for posit arithmetic! HiPEAC is…
News Espressif Reveals ESP32-P4: A High-Performance MCU with Numerous IO-Connectivity and Security Features | Espressif SystemsEspressif Systems (SSE: 688018.SH) today announces the upcoming release of its latest SoC, ESP32-P4. It is powered by a dual-core RISC-V CPU with an AI…
Ventana Introduces CES Audience to World’s Highest Performance RISC-V CPU, Veyron V1 | Ventana Micro SystemsVentana Micro Systems announced that it will be presenting at the Consumer Electronics Show being held in Las Vegas (CES) between Jan. 5-8 the Veyron V1, the first RISC-V…
A Bottom-Up Methodology for the Fast Assessment of CNN Mappings on Energy-Efficient Accelerators | Guillaume Devic, Gilles Sassatelli and Abdoulaye GamatiéAbstract - The execution of machine learning (ML) algorithms on resource-constrained embedded systems is very challenging in edge computing. To address this issue, ML accelerators…
Ventana Introduces CES Audience to World’s Highest Performance RISC-V CPU, Veyron V1 | Ventana Micro Systems, Yahoo! FinanceVentana Micro Systems Inc. announced today that it will be presenting at the Consumer Electronics Show being held in Las Vegas (CES) between Jan. 5-8 the Veyron V1, the first…
RISC-V could become a first-class citizen for Android, Pixel 7a hands-on video leaked, and GeForce Now adds a RTX 4080 tier | Brad Linder, LiliputingRISC-V is an open, royalty-free chip architecture positioned as an alternative to the ARM and x86 chips that dominate the PC, mobile, server, and embedded…
Breker Verification Systems Unveils Easy-To-Adopt Integrity FASTApps Targeting RISC-V Processor Core, SoC Verification Scenarios | Breker Verification SystemsAutomated Test Generation Verification IP Elements Focus on Difficult Scenarios for Broad Range of Processor Cores and SoCs. Breker Verification Systems, the leading provider of…
Google wants RISC-V to be a “tier-1” Android architecture | Ron Amadeo, Ars TechnicaGoogle's keynote at the RISC-V Summit promises official, polished support. Over the holiday break, the footage from the recent "RISC-V Summit" was posted for the world to…
RISC-V Summit 2022: All Your CPUs Belong to Us | Kevin Krewell, EE TimesIn a recent guest editorial here on EE Times, legendary professor David Patterson wrote about busting the five myths around the RISC-V instruction set architecture (ISA). At…