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Launch of the New Horizon Europe Project SYCLOPS
Sipeed Teases a $40 Single-Board Computer with Fully-Ratified RISC-V Vector Extensions
[PODCAST] Memory Allocation, Digital-Friendly Analog and Configurable 64-bit RISC-V
RISC-V ratifies compressed instruction extensions
Wearable Payment Solution Based On T-Head Security Technologies
Community Growth in India through Vegathon Events | RISC-V International
Tenstorrent Selects Arteris IP for HPC RISC-V ChipletsCharles Lohr Turns a $0.10 RISC-V Microcontroller Into a “Software-Defined Flyback” for Nixie Tubes
Tenstorrent Selects Arteris IP for AI HPC and Datacenter RISC-V ChipletsMenta, Codasip join RISC-V 3D neuromorphic AI project
Making Developers the Protagonists: 2023 RT-Thread Global Tech Conference Registration Opens.
RISC-V’s Worldwide Expansion and Andes Technology’s Contribution
Ox64 SBC powered by dual RISC-V processors | Giorgio Mendoza, Linux Gizmos
Google shows off KataOS, a secure operating system written in Rust | Liam Tung, ZDNETIAR boosts its automotive RISC-V support | Nick Flaherty, EE News EuropeAndes claims first RISC-V CPU IP with full ISO 26262 compliance, plans DSP version | Nick Flaherty, EE News Europe
What Is RISC, What Is RISC V, and How Do They Differ? | Arol Wright, Make Use Of
First RISC-V laptop uses Alibaba TH1520 SoC | Nitin Dahad, EmbeddedFrench secure element processor uses RISC-V | Nick Flaherty, EE News Europe
RISC-V Virtual Prototype | Pieper, P.; Herdt, V.; Drechsler, R., Semiconductor Engineering
Intel demos “Horse Creek” developer board with SiFive RISC-V CPU, DDR5 RAM and PCIe 5.0 slot | Bogdan Solca, Notebook Check
Andes Technology Announces Return of the Annual RISC-V CON on October 18th in the San Jose Airport DoubleTree Hotel | Andes Technology
Alibaba RISC-V SoC Revealed as Processor for First RISC-V Laptop | Jake Hertz, All About Circuits
Intel Horse Creek platform showcased with SiFive P550 RISC-V CPU, 8GB DDR5, PCIe Gen5 | Jean-Luc Aufranc, CNX Software
Launch of the New Horizon Europe Project SYCLOPS8 leading European organisations join forces to bring together RISC-V and SYCL standards to demonstrate ground-breaking advances in scalability of extreme data analytics via fully-open…
Sipeed Teases a $40 Single-Board Computer with Fully-Ratified RISC-V Vector ExtensionsSipeed has posted images teasing a new single-board computer based on a RISC-V processor boasting the ratified RISC-V Vector Extension 1.0 — something which should…
[PODCAST] Memory Allocation, Digital-Friendly Analog and Configurable 64-bit RISC-VIn this edition of Embedded Edge with Nitin, there’s a bit of a RISC-V theme: I talk to SemiDynamics, a configurable 64-bit RISC-V startup coming…
RISC-V ratifies compressed instruction extensionsRISC-V has ratified its extensions for code compression to reduce the memory requirements when using the open instruction set architecture. This is particularly important for…
Wearable Payment Solution Based On T-Head Security TechnologiesBy Xiaoxia Cui Wearable devices, such as smartwatches and pulse oximeters, are gaining popularity with the continuous expansion of IoT applications in recent years. However,…
Community Growth in India through Vegathon Events | RISC-V InternationalThirty hours! That’s how long some of the recent VEGA Processors hackathons, VEGATHON, have lasted. At a recent hackathon local RISC-V enthusiasts used the RISC-V-based…
Tenstorrent Selects Arteris IP for HPC RISC-V ChipletsCAMPBELL, Calif. – May 2, 2023 – Arteris, Inc. (Nasdaq: AIP), a provider of system IP designed to accelerate system-on-chip (SoC) creation, today announced that…
Charles Lohr Turns a $0.10 RISC-V Microcontroller Into a “Software-Defined Flyback” for Nixie TubesYouTuber Charles Lohr has come up with a novel and low-cost way to drive Nixie display tubes, turning an ultra-low-cost RISC-V microcontroller into what he…
Tenstorrent Selects Arteris IP for AI HPC and Datacenter RISC-V ChipletsCAMPBELL, Calif., May 2, 2023 — Arteris, Inc., a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced Tenstorrent has licensed Ncore…
Menta, Codasip join RISC-V 3D neuromorphic AI projectThe research wing of European RISC-V processor core developer Codasip and French embedded FPGA firm Menta have joined a project to build a 3D neuromorphic…
Making Developers the Protagonists: 2023 RT-Thread Global Tech Conference Registration Opens.The RT-Thread Global Tech Conference (RGTC) is an annual event that brings together developers from around the world to focus on the latest developments in…
RISC-V’s Worldwide Expansion and Andes Technology’s ContributionA Q&A with Andes’ Board of Directors’ Advisor Charlie Cheng, Managing Director of Polyhedron. What is Andes Technology and how has it grown in…
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Ox64 SBC powered by dual RISC-V processors | Giorgio Mendoza, Linux GizmosPine64 announced a few days ago their latest SBC based on a dual-core RISC-V processor. The compact Ox64 is enabled with Wi-Fi 4.0, Zigbee BL5.0…
Google shows off KataOS, a secure operating system written in Rust | Liam Tung, ZDNETSmart devices need better security and Google thinks KataOS, written in the Rust programming language, could help. Google has unveiled KataOS, an early exploration into…
IAR boosts its automotive RISC-V support | Nick Flaherty, EE News EuropeIAR Systems has added support for the latest RISC-V automotive CPU IP from SiFive to its embedded tools. The IAR Embedded Workbench for RISC-V now…
Andes claims first RISC-V CPU IP with full ISO 26262 compliance, plans DSP version | Nick Flaherty, EE News EuropeAndes Technology has launched a safety-enhanced 32bit RISC-V CPU IP that it says is the first to be certified as fully compliant with ISO 26262…
What Is RISC, What Is RISC V, and How Do They Differ? | Arol Wright, Make Use OfWhen talking about processors, x86 and ARM are the two terms that come up the most, especially if we're talking about recent devices. But there…
First RISC-V laptop uses Alibaba TH1520 SoC | Nitin Dahad, EmbeddedEarlier this month RISC-V International announced that ROMA, claimed to be the world’s first native RISC-V development laptop, is powered by Alibaba T-Head’s TH1520 system-on-chip…
French secure element processor uses RISC-V | Nick Flaherty, EE News EuropeFrench processor designer Tiempo Secure has developed secure IP based on the RISC-V open instruction set. The TESIC Secure Element IP uses the RV32IMCB 32bit…
RISC-V Virtual Prototype | Pieper, P.; Herdt, V.; Drechsler, R., Semiconductor EngineeringA new technical paper titled “Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype” was published by researchers at DFKI GmbH…
Intel demos “Horse Creek” developer board with SiFive RISC-V CPU, DDR5 RAM and PCIe 5.0 slot | Bogdan Solca, Notebook CheckThe Horse Creek board features a SoC with 4x SiFive P550 cores manufactured on the Intel 4 production nodes. Intel integrated 8 GB of DDR5-5600…
Andes Technology Announces Return of the Annual RISC-V CON on October 18th in the San Jose Airport DoubleTree Hotel | Andes TechnologySan Jose, Oct. 10, 2022 (GLOBE NEWSWIRE) -- Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit…
Alibaba RISC-V SoC Revealed as Processor for First RISC-V Laptop | Jake Hertz, All About CircuitsAlibaba's RISC-V SoC will power the ROMA development laptop, the industry’s first RISC-V offering. Of all the developments in the computing industry, the RISC-V movement…
Intel Horse Creek platform showcased with SiFive P550 RISC-V CPU, 8GB DDR5, PCIe Gen5 | Jean-Luc Aufranc, CNX SoftwareWhen SiFive introduced its Performance P550 64-bit RISC-V processor in 2021, we were told that Intel would use it in the Horse Creek platform with “leading-edge interface…