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SiFive, Intel Announce HiFive Pro P550 MicroATX RISC-V Development Board
The First DSA Agile Development on Open Xuantie RISC-V processor
SiFive HiFive Pro P550 dev board coming this summer with Intel “Horse Creek” RISC-V chip
HPMicro HPM64G0 – A 1 GHz RISC-V microcontroller
Selecting The Right RISC-V Core | Brian Bailey, Semiconductor Engineering
Risc-V MCUs have 8 to 20 pins
Late Night Linux – Episode 212
Bluespec collaborates with Synopsys to address growing verification demands for RISC-V design communityBluespec collaborates with Synopsys to address growing verification demands for RISC-V design communityEEVblog 1524 – The 10 CENT RISC V Processor! CH32V003Selecting The Right RISC-V Core$4 Sipeed M0S Dock IoT development board features BL616 WiFi 6, BLE 5.2, and Zigbee RISC-V microcontroller
Microchip to develop next generation 12 core RISC-V space processor for NASA | Nick Flaherty, EE News Europe
Latest Funding Drives Ventana’s First RISC-V Chiplets in Data Centers | Nitin Dahad, EE Times
2022 RISC-V Taipei Day to be held in September to explore RISC-V driven developments in EV, smart vehicles | DigiTimes AsiaLatest Funding Drives Ventana’s First RISC-V Chiplets in Data Centers | Nitin Dahad, EE Times
RISC-V Summit China 2022 Announces Agenda | Inside HPC
Case study: optimizing PPA with RISC-V custom extensions in TWS earbuds | John Minh, Andes TechnologiesDAC – where RISC-V thrives and mixed signal design blends in | EW Staff, Electronics Weekly
Imperas leads the RISC-V verification ecosystem as the first to release an open-source SystemVerilog RISC-V processor functional coverage library | Imperas Software
SiFive Is Leading The Way For Innovation On RISC-V | Karl Freund, Forbes
Chips and the Open-Source Secret | Isabella Borshoff, The Wire ChinaNordic Semi sets up RISC-V design team | Nick Flaherty, EE News EuropeRISC-V verification ecosystem releases complete source file access | Imperas Software, Electropages
SiFive, Intel Announce HiFive Pro P550 MicroATX RISC-V Development BoardWe are now learning new details on the fruits of the partnership between SiFive and Intel. The two companies have announced that the HiFive Pro P550 development board…
The First DSA Agile Development on Open Xuantie RISC-V processorAuthor: Prof. Jun Han, Fudan University T-Head made the Xuantie RISC-V series processors open-source and made a series of tools and system software available at…
SiFive HiFive Pro P550 dev board coming this summer with Intel “Horse Creek” RISC-V chipIntel is best known for its x86 processors, but last year the company announced it was teaming up with RISC-V chip designed SiFive to release a “Horse…
HPMicro HPM64G0 – A 1 GHz RISC-V microcontrollerYesterday, I ended up on the HPMicro website showing the illustration above about a 1 GHz MCU called HPM64G0. It looked interesting enough so I…
Selecting The Right RISC-V Core | Brian Bailey, Semiconductor EngineeringWith an increasing number of companies interested in devices based on the RISC-V ISA, and a growing number of cores, accelerators, and infrastructure components being…
Risc-V MCUs have 8 to 20 pinsCalled the CH32V003 series, they are based on the company’s own QingKe RISC-V2A core with a hardware interrupt stack and two-level interrupt nesting, supported by…
Late Night Linux – Episode 212The rise of RISC-V continues apace, we bust a recent ZFS myth, hybrid tiling in Plasma, Stadia departs with a nice gift for people, Joe…
Bluespec collaborates with Synopsys to address growing verification demands for RISC-V design communityIndustry-leading Synopsys VCS simulation and Verdi hardware/software debug solutions accelerate verification and validation of RISC-V cores FRAMINGHAM, MASS. (PRWEB) JANUARY 11, 2023 Bluespec Inc., announced today…
Bluespec collaborates with Synopsys to address growing verification demands for RISC-V design communityIndustry-leading Synopsys VCS simulation and Verdi hardware/software debug solutions accelerate verification and validation of RISC-V cores FRAMINGHAM, MASS. (PRWEB) JANUARY 11, 2023 Bluespec Inc., announced today…
EEVblog 1524 – The 10 CENT RISC V Processor! CH32V003Checking out the new 10 cent WCH CH32V003 48MHz RISC V processor demo board and the MounRiver Eclipse IDE. Getting to blinky. The CH32V003 is…
Selecting The Right RISC-V CoreWith an increasing number of companies interested in devices based on the RISC-V ISA, and a growing number of cores, accelerators, and infrastructure components being…
$4 Sipeed M0S Dock IoT development board features BL616 WiFi 6, BLE 5.2, and Zigbee RISC-V microcontrollerAs expected, Sipeed has now launched the Sipeed M0S IoT module based on Bouffalo Lab BL616 RISC-V microcontroller with 2.4 GHz WiFi 6, BLE 5.2,…
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Microchip to develop next generation 12 core RISC-V space processor for NASA | Nick Flaherty, EE News EuropeMicrochip has won a $50m project to develop the next generation of high reliability processor for space missions based on RISC-V technology with European engineers.…
Latest Funding Drives Ventana’s First RISC-V Chiplets in Data Centers | Nitin Dahad, EE TimesEver since Ventana Micro Systems came out of stealth last year, the company has been busily developing relationships with partners and potential customers to create traction for…
2022 RISC-V Taipei Day to be held in September to explore RISC-V driven developments in EV, smart vehicles | DigiTimes AsiaAccording to the semiconductor research company IC Insights, the global MCU revenue in 2022 will reach US$21.5 billion and the growth of automotive MCUs will…
Latest Funding Drives Ventana’s First RISC-V Chiplets in Data Centers | Nitin Dahad, EE TimesEver since Ventana Micro Systems came out of stealth last year, the company has been busily developing relationships with partners and potential customers to create traction for…
RISC-V Summit China 2022 Announces Agenda | Inside HPCThe RISC-V Summit China 2022 (Aug. 24-26) today announced its 2022 agenda, including keynotes, tutorials, and technical presentations in English language and Chinese language editions. This year’s…
Case study: optimizing PPA with RISC-V custom extensions in TWS earbuds | John Minh, Andes TechnologiesA common goal for many IC designs is achieving an optimum combination of power, performance, and area (PPA). This article examines the components and design…
DAC – where RISC-V thrives and mixed signal design blends in | EW Staff, Electronics WeeklyAt last month’s 59th DAC (Design Automation Conference), a significant announcement was made by Siemens Digital Industries Software. Acknowledging the growth of mixed signal design,…
Imperas leads the RISC-V verification ecosystem as the first to release an open-source SystemVerilog RISC-V processor functional coverage library | Imperas SoftwareComplete source file access allows easy adoption and enables user extensions for advanced microarchitecture verification that helps all RISC-V projects accelerate time-to-market goals. Imperas Software…
SiFive Is Leading The Way For Innovation On RISC-V | Karl Freund, ForbesThe company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU…
Chips and the Open-Source Secret | Isabella Borshoff, The Wire ChinaAs China pushes for semiconductor self-sufficiency, it’s found an unlikely ally: an international foundation dedicated to open source technology, with its origins in California’s libertarian…
Nordic Semi sets up RISC-V design team | Nick Flaherty, EE News EuropeLeading European chip design Nordic Semiconductor is setting up a new design team to develop a processor core based on the open RISC-V instruction set.…
RISC-V verification ecosystem releases complete source file access | Imperas Software, ElectropagesImperas Software Ltd has released the first open-source SystemVerilog RISC-V processor functional coverage library for RISC-V cores. This initial release is for RV32IMC and RV64.…