By: Nick Brown, EPCC High Performance Computing (HPC) is one of the most exciting and challenging fields, solving the world's biggest problems with incredible levels of processing power. With an…
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Introduction Following the gap analysis done in the second half of 2023, the Vector Special Interest Group (SIG-Vector) has been working on specifying instructions to accelerate matrix operations. Two Task…
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Abstract The European Processor Initiative (EPI) is a project dedicated to developing a general-purpose processor and an accelerator, alongside the necessary software layers for their integration into the High Performance…
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S2C Launches Prodigy S8-100 Series: 100M Gate FPGA Prototyping for AI and HPC December 19, 2024 – S2C, a global leader in FPGA-based prototyping solutions, announces its Prodigy S8-100 Logic…
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RISC-V is an open Instruction Set Architecture (ISA), where the ISA can be thought of as the contract between the software and hardware worlds. Since RISC-V was first released around a decade…
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MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Esperanto Technologies™, a leading developer of RISC-V chips and software for high-performance computing (HPC) and artificial intelligence (AI), today announced that they are cooperating with NEC Corporation…
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Learn how designers benefit from the combination of TASKING's VX Toolset for RISC-V and Synopsys ARC-V™ IP, by gaining access to tools to develop safe, secure, and power-efficient SoCs for…
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As RISC-V gains traction as an open-source alternative to Arm, several companies have announced partnerships and research to bolster the ISA. Forecasts show that AI will continue to fuel RISC-V…
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By Nick Brown, Senior Research Fellow at EPCC, University of Edinburgh May the 13th saw the commencement of the 39th International Supercomputing Conference (ISC) in sunny Hamburg. With almost…
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