Blog

Dec 20, 2024

Exploring RISC-V ISA Developments and Technical Highlights from 2024

Dec 19, 2024

RISC-V 2024: A Year of Global Growth and Innovation

Dec 17, 2024

Longnail: Hardware Synthesis of CoreDSL Custom Instructions for MCU- and Application-Class Cores

Dec 17, 2024

My Journey with the RISC-V Mentorship | Sailing Downstream II

Dec 13, 2024

XuanTie Co-Processor Interface Solution: A Bridge to Efficient Collaborative Computing

Nov 22, 2024

Enhancing the Future of AI/ML with Attached Matrix Extension

Nov 20, 2024

Meet Andrea Gallo, RVFA: A Senior IT Leader’s Career Pivot

Nov 15, 2024

Triton kernel performance on RISC-V CPU

Nov 8, 2024

Stream Computing Provides Smart Community Services Based on RISC-V Computing Power and LLMs

Nov 7, 2024

Stream Computing RISC-V Matrix Extension Open Source Project Upgrades to Version 0.5, Supporting Vector+Matrix Implementation

Nov 6, 2024

Real-Time, Zero-Trust Cybersecurity for the PolarFire® SoC and IoT

Nov 4, 2024

How to Share Your Work and See What Others Are Building On RISC-V

Oct 29, 2024

RISC-V Forum Shenzhen: Unleashing Power of Electronics Making to Lead Global Open-Source Innovations

Oct 11, 2024

Chile’s First Steps with RISC-V: Paving the Way for Technological Innovation

Oct 11, 2024

RISC-V Summit North America 2024: Keynotes and Industry Tracks

Oct 9, 2024

Don’t Miss Out: RISC-V Summit North America 2024 – Register Before Prices Increase!

Oct 8, 2024

Towards Generic RISC-V TEE Ecosystem with Penglai and OP-TEE

Oct 8, 2024

AI/ML Innovations at RISC-V Summit North America: A Track to Watch

Oct 1, 2024

Join Us for the RISC-V Hackathon at Summit North America 2024!

Sep 27, 2024

RISC-V Processor Design – Free YouTube Course by Maven Silicon

Sep 27, 2024

Get Started With Real-Time Systems Using Microchip’s PolarFire® SoC FPGA and TASKING Debug and Analyze Tools

Sep 27, 2024

Debugging of PolarFire® SoC FPGAs Made Easy with Lauterbach’s TRACE32® Tools

Sep 27, 2024

Box64 Adds Initial Support for RISC-V Vector 1.0 (RVV) Extension, Achieves up to 300% Performance Boost, Code Now Open-Source and Merged Upstream

Sep 26, 2024

TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor

Sep 25, 2024

Rivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoC

Sep 17, 2024

Leveraging a Passion for Logic into a RISC-V Career

Sep 9, 2024

Advancing AI the Brazilian Way: Fostering Innovation Through Collaboration and Open Standards

Sep 6, 2024

Hot Chips and Even Hotter Connections: RISC-V is Everywhere!

Sep 5, 2024

Trailblazers: Board of Directors Software Award Winners 2024

Sep 3, 2024

STMicroelectronics Joins Quintauris as Sixth Shareholder

Aug 29, 2024

Exploring the Amazing RISC-V Summit China 2024

Aug 28, 2024

Introducing the Newly Elected RISC-V Board of Directors Officers and Members

Aug 27, 2024

RISC-V SoC Design Workshop by Maven Silicon in Malaysia & Singapore

Aug 27, 2024

RISC-V Summit North America T-Shirt Design Contest—And the Winner Is…!

Aug 26, 2024

CHERIoT: A Study in CHERI

Aug 23, 2024

Join the ranks of RISC-V Advocates!

Aug 22, 2024

Infineon Harnesses the Power of RISC-V for Next-Generation Automotive MCU Innovation

Aug 22, 2024

Featured Work: Microarchitecture Security: The Spectre Affair

Aug 20, 2024

Unlocking the Potential of Your RISC-V Laptop: The DC-ROMA Laptop II

Aug 20, 2024

Exploring the RISC-V Summit 2024: Technical Sessions Announced

Aug 14, 2024

Trailblazers: Board of Directors Technical Award Winners 2024

Aug 13, 2024

SpacemiT Key Stone K1 AI CPU has been adapted to the Fedora

Aug 12, 2024

More than 1,300 Attendees Expected at RISC-V Summit China Next Week

Aug 8, 2024

Microchip, and O.C.E. Technology deliver high-reliability RTOS for Polarfire® SoC FPGA space applications

Aug 6, 2024

Open source System on Module with Microchip PolarFire SoC

Jul 31, 2024

Defining RISC-V CPUs in Renode simulation with custom instructions and extensions

Jul 29, 2024

Debugging of RISC-V-Based Chips Made Easy

Jul 26, 2024

New Launch: Advanced RISC-V Courses | Maven Silicon

Jul 22, 2024

How ChipFlow is Making the Impossible Possible

Jul 12, 2024

RT-Thread: Pioneering Real-Time Operating System for RISC-V

Jul 1, 2024

METASAT Project Celebrates 18 Months of Innovation: Key Developments in Satellite Technology

Jun 28, 2024

Stream Computing partners with VRULL and Software Ecosystems Solutions to build a richer software ecosystem for RISC-V AI application

Jun 26, 2024

Accelerate RISC-V Verification Using Synopsys Cloud

Jun 25, 2024

RISC-V Summit Europe is Underway with 700+ Attendees Representing 40 Countries

Jun 23, 2024

AI, Collaboration, Security and More: Women Speak on Key Topics at RISC-V Summit International

Jun 20, 2024

RISC-V in Brazil: Leading the Open Compute Era in Latin America

Jun 10, 2024

HPC on RISC-V a hot topic at the International Supercomputing Conference, Hamburg

Jun 7, 2024

My Top 10 Reasons to Attend RISC-V Summit Europe

Jun 6, 2024

Designing with RISC-V Using ChipInventor

Jun 5, 2024

RISC-V Summit China 2024: Details Now Available on Call for Proposals and Sponsorships

May 31, 2024

Seeking Sponsors for RISC-V Day Tokyo 2024!

May 30, 2024

UNVEILING THE TASKING RISC-V COMPILER | A Breakthrough regarding the development of FuSa and Cybersecurity compliant Software.

May 17, 2024

Keynote: Charting the AI-Powered Transformation in the Semiconductor Industry

May 14, 2024

14 Years of RISC-V: A Journey of Innovation and Firsts

May 9, 2024

Recent developments in the Zephyr port for RISC-V

Apr 25, 2024

RISC-V Impact on Technology and Innovation

Apr 24, 2024

RISC-V for All!

Apr 22, 2024

Exploring the Top Highlights of the RISC-V Booth at embedded world 2024

Apr 18, 2024

Celebrating Women in the Global RISC-V Community

Apr 10, 2024

Introducing SoM1-SOC: The Most Powerful SoM Based on PolarFire® SoC FPGA

Apr 10, 2024

Integrated IP Core Generation Workflow for Microchip SoC FPGAs With MathWorks®

Apr 9, 2024

Meeting RISC-V Demands: S2C’s Tailored Offerings

Apr 5, 2024

Visit RISC-V at embedded world 2024!

Apr 4, 2024

RISC-V Technical Leadership Update

Apr 3, 2024

Java 21 and 22 Now Available on RISC-V: A Collaboration Between RISE and Eclipse Adoptium

Apr 3, 2024

Empower Innovation with Numato Lab’s EagleCore™ PolarFire® SoC FPGA SOM

Apr 3, 2024

MontaVista Software: Carrier Grade eXpress (CGX) 4.0 on Microchip PolarFire® SoC FPGA

Mar 26, 2024

Ensuring Integrity: The Role of SoC Security in Today’s Digital World

Mar 21, 2024

BRAZIL AND EUROPE SIGN INNOVATIVE PROJECT WITH RISC-V TECHNOLOGY FOR HPC

Mar 15, 2024

Advanced RISC-V Training Course | Maven Silicon – RISC-V Global Training Partner

Mar 15, 2024

Introducing the RISC-V Enterprise Software Ecosystem Dashboard

Mar 14, 2024

Securing software execution with CHERI on a Codasip A730 RISC-V core

Mar 14, 2024

SiFive Upgrades Automotive Security for the RISC-V Ecosystem with New ISO/SAE 21434 Certification

Mar 11, 2024

Adding Physical Memory Protection to the VeeR EL2 RISC-V Core

Mar 8, 2024

Spotlighting Women in the Global RISC-V Community this International Women’s Day

Feb 27, 2024

Soccer, Chips, RISC-V and Brazil

Feb 26, 2024

Porting and Optimizing Android ART on XuanTie C910

Feb 26, 2024

Developing and testing heterogeneous space-grade systems with Renode

Feb 21, 2024

Feb 19, 2024

Announcing The Fourth International Workshop on RISC-V for HPC

Feb 13, 2024

Integrating ROS 2 With Microchip’s PolarFire® SoC FPGA

Feb 12, 2024

OPC UA on PolarFire SoC: Enabling Industrial Edge Solutions

Jan 8, 2024

The Rise of RISC-V – Analyzing Market Trends and Ecosystem Dynamics

Jan 4, 2024

Expanding RISC-V support in Renode with Bit-Manipulation extensions

Dec 15, 2023

Five years of SERVing

Dec 13, 2023

The Top 10 RISC-V Milestones & Highlights from 2023

Dec 12, 2023

Developing and testing with Renode in heterogeneous, multi-node automotive use cases

Dec 12, 2023

Solving bus and software deadlock problems in complex SoCs

Dec 8, 2023

RISC-V Summit 2023: RISC-V is Here for Developers!

Dec 1, 2023

World’s First RISC-V Pad with LTE Launched by DeepComputing at RISC-V Summit 2023

Nov 30, 2023

Enabling Secure Open Source ML Products with Open Se Cura

Nov 28, 2023

Integrating PikeOS with Microchip’s RISC-V based PolarFire® SoC FPGA | PikeOS: A Versatile Hypervisor-RTOS

Nov 16, 2023

[Case Study] SuperTest – helping TrustInSoft guarantee its customers 100% bug-free source code

Nov 15, 2023

Quick Time-To-Market with a Compact and Powerful Microchip PolarFire® SoC FPGA System on Module

Nov 7, 2023

Accelerating the Open Source Software Ecosystem with RISC-V Labs

Nov 3, 2023

Debugging RISC-V processors using E-Trace

Nov 2, 2023

S2C’s FPGA Prototyping Accelerates Iterations of XiangShan RISC-V Processor

Oct 31, 2023

RISC-V is Here! RISC-V Summit North America Showcases Innovation, Products, Boards, Community

Oct 13, 2023

Journeying Beyond AI: Unleashing the Art of Verification

Oct 11, 2023

DPI support in Renode for HDL co-simulation with Verilator and Questa

Oct 9, 2023

RISC-V: An Open Standard – Backed by a Global Community – to Enable Open Computing for All

Sep 28, 2023

Acura, part of HID, Collaborates with Von Braun Labs and #Data to Develop a RISC-V Based ASIC for Access Control and Free-Flow Tolling

Sep 25, 2023

It’s not just about the core, it’s also about the system

Sep 21, 2023

How to Design a RISC-V Space Microprocessor

Sep 7, 2023

DeepComputing Has Made Great Processes in New Hardware Devices and Software Solutions

Aug 31, 2023

Introducing the RISC-V Board of Directors Elected Officers

Aug 30, 2023

RISC-V co-design using trace-based simulation with Renode and TBM

Aug 27, 2023

RISC-V Public Beta Platform Release · Database Adaptation Evaluation On RISC-V server

Aug 27, 2023

Debugging a RISC-V processor requires integrated hardware and software tools

Aug 24, 2023

Cloud-V: Accelerating RISC-V Software Development with 10xEngineers

Aug 17, 2023

Oral History of Mark Himelstein | CTO of RISC-V International

Aug 15, 2023

Cool PolarFire® SoC FPGA Based System On Modules by ARIES Embedded

Aug 14, 2023

RISC-V Expanding In China

Aug 10, 2023

XuanTie RISC-V Contest on Innovation of Applications

Aug 4, 2023

Why Innovation in Analog IP is so Important for the RISC-V Ecosystem

Aug 1, 2023

RISC-V Summit China 2023 | August 23-25

Jul 28, 2023

Witnessing the Power of RISC-V at My First DAC

Jul 26, 2023

The release of the first two mass-produced development boards – AOSP powered by TH1520 SoC

Jul 24, 2023

Why Maven Silicon for Upskilling Your Chip Design Workforce?

Jul 24, 2023

Ashling RiscFree™ C/C++ SDK support for the Zephyr Real-Time Operating System (RTOS)

Jul 20, 2023

The Power of RISC-V: DAC Panel with Intel, Imperas, Meta, OpenHW Group & Ventana

Jul 19, 2023

The Growing Momentum of RISC-V in Europe

Jul 19, 2023

YOLOX for Object Detection

Jul 19, 2023

SiFive’s WorldGuard Security Platform Now Available to the Entire RISC-V Ecosystem

Jul 14, 2023

Ashling announces RiscFree™ C/C++ SDK support for Lattice RISC-V MCU CPU Soft IP Cores

Jul 13, 2023

The Incredible Growth of RISC-V in India

Jul 11, 2023

Open Source and CI-driven RTL Testing and Verification for Caliptra’s RISC-V VeeR Core

Jul 6, 2023

RISC-V Summit Europe 2023: Highlights from Barcelona

Jun 28, 2023

The Call for Papers for RISC-V Summit China 2023 is Open

Jun 25, 2023

GreenRio: A Linux-Compatible RISC-V Processor Designed for Open-Source EDA Implementations

Jun 22, 2023

Addition of Single Precision Floating Point (F) extension in NucleusRV: RISC-V based RV32-IMC Core

Jun 19, 2023

When tapas meet tech: Barcelona’s RISC-V Summit feeds our appetite for innovation

Jun 14, 2023

Integrating Tile Link UH in the Caravan Framework: A Journey of Enhanced Functionality

Jun 7, 2023

Safety Critical Real-Time Operating System, SAFERTOS® Available With MiV_RV32 Soft CPU

Jun 5, 2023

SOPHGO Donates 50 RISC-V Motherboards – Learn More About the Pioneer Box

Jun 1, 2023

NOEL-V Processor’s Security Extensions for Safe and Secure Computing

May 25, 2023

NOEL-V: A RISC-V Processor for High-Performance Space Applications

May 24, 2023

RISC-V: An Open Standard Instruction Set Architecture

May 22, 2023

RISC-V Announces Agenda for 2023 RISC-V Summit Europe

May 22, 2023

RISC-V and the Future of Machine Learning Computing

May 18, 2023

Co-developing RISC-V AI solutions using Vector Extensions in Renode with Kenning

May 18, 2023

T-Head Prototypes Innovative Hardware Support for Virtual IOMMU

May 15, 2023

[INTERVIEW] Calista Redmond, RISC-V International | Open Source Summit NA 2023

May 15, 2023

How to Speed Up the Emulating Process with Pydrofoil | Carl Friedrich and Matti Picus

May 15, 2023

Chip War Without Soldiers

May 10, 2023

[WEBINAR] Taking the Risk out of Developing Your Own RISC-V Processor with Fast, Architecture-Driven, PPA Optimization

May 10, 2023

Canonical enables Ubuntu on StarFive’s VisionFive 2 RISC-V single board computer

May 3, 2023

Wearable Payment Solution Based On T-Head Security Technologies

May 2, 2023

Community Growth in India through Vegathon Events | RISC-V International

Apr 26, 2023

RISC-V’s Worldwide Expansion and Andes Technology’s Contribution

Apr 18, 2023

Accelerate Your Success by Joining RISC-V Membership

Apr 18, 2023

Raising RISC-V processor quality with formal verification

Apr 3, 2023

Adapting OpenTitan for open source FPGA prototyping and tooling development

Apr 3, 2023

[PODCAST] Making Formal Verification the New Normal in IoT with Ashish Darbari – Founder, Axiomise | The IoT Podcast

Apr 2, 2023

Announcing the Nerds Talking to Nerds About RISC-V event hosted by Tenstorrent | Tenstorrent

Mar 31, 2023

A dual-core TEE security solution based on E902

Mar 28, 2023

Canonical Enables Ubuntu on Microchip’s PolarFire® SoC FPGA

Mar 24, 2023

Catch up with the best of the RISC-V booth from Embedded World 2023

Mar 22, 2023

Top Ten Fallacies About RISC-V

Mar 21, 2023

Tiempo Secure brings additional security features to the RISC-V ecosystem

Mar 21, 2023

The Evolving Automotive Experience Made Possible by RISC-V

Mar 13, 2023

Why we’ve levelled up on RISC-V

Mar 10, 2023

MachineWare at Embedded World 2023

Mar 10, 2023

Empowering RISC-V with open source innovation from Ubuntu

Mar 10, 2023

First Xuantie Partner Conference in China Highlights Growth Momentum of Thriving RISC-V Community

Mar 9, 2023

What to see at Embedded World 2023

Mar 7, 2023

RISC-V Webinar with Andes and Imperas: “RISC-V Design Innovations with Custom Extensions.”

Feb 24, 2023

Maven Silicon’s RISC-V Processor IP Verification Flow

Feb 21, 2023

Porting NuttX Real-Time Operating System on PolarFire® SoC FPGA

Feb 14, 2023

Announcing The First International Workshop for HPC based on RISC-V

Feb 10, 2023

XuanTie Matrix Multiply Extension Instructions

Feb 10, 2023

TEE SoC Based on RISC-V

Feb 7, 2023

CPU RTL co-simulation in Renode

Jan 25, 2023

Xuantie RISC-V TEE solution for MCU

Jan 24, 2023

RISC-V RV32I RTL Verification using UVM | Maven Silicon Blog

Jan 20, 2023

The First DSA Agile Development on Open Xuantie RISC-V processor

Jan 12, 2023

The RISC-V Mentorship Program – a 2022 Recap, What’s to Come for 2023, and How to Apply

Jan 12, 2023

Support for Microchip’s RISC-V Platforms in Antmicro’s Open-Source Renode Framework and Beyond

Jan 11, 2023

RISC-V Celebrates Momentum of 2022 and Accelerating Adoption in 2023

Jan 11, 2023

RISC-V Celebrates Momentum of 2022 and Accelerating Adoption in 2023

Jan 4, 2023

Run 32-bit applications on 64-bit Linux kernel | LIU Zhiwei, GUO Ren| T-Head Division of Alibaba Cloud

Jan 4, 2023

SpacemiT Makes Important Breakthroughs in RISC-V High-Performance Cores | SpacemiT

Jan 2, 2023

StarFive Releases StarFive StarStudio IDE, which supports both Linux and Baremetal Development | StarFive

Jan 1, 2023

How to Deploy a Neural Network on TH1520 | Wenmeng Zhang, Alibaba Cloud

Dec 20, 2022

XuanTie C908 Accelerates AI with Software and Hardware Fusion

Dec 6, 2022

RISC-V Based IoT Platform Development Using Green Hills Software

Dec 5, 2022

INTEL PATHFINDER FOR RISC-V: NEW CAPABILITIES AND A GROWING ECOSYSTEM | Intel Corporation

Dec 5, 2022

Is your career at RISK without RISC-V? | P R Sivakumar, Founder and CEO, Maven Silicon

Dec 1, 2022

RISC-V Summit 2022: Future Careers Start Here

Nov 30, 2022

RISC-V Summit 2022: A Journey from Android to Outer Space … and Much More | RISC-V International

Nov 24, 2022

2022 RISC-V Summit Technical Tutorials Announced | RISC-V International

Nov 3, 2022

XuanTie C908: High-performance RISC-V Processor Catered to AIoT Industry | Chang Liu, Alibaba Cloud

Nov 2, 2022

Registration for the In-person RVfpga Session at the 2022 RISC-V Summit is Open. Space is Limited! | Imagination Technologies

Oct 25, 2022

InspireSemi to Ring the Toronto Stock Exchange Closing Bell on October 25 | InspireSemi

Oct 23, 2022

First Patches from Alibaba Cloud Enable Android Open Source Project on RISC-V | Han Mao and David Chen, Alibaba Cloud

Oct 23, 2022

RISC-V Celebrates Upstreaming of Android Open Source Project RISC-V Port | RISC-V International

Oct 12, 2022

Tiempo Secure becomes a Strategic Member of RISC-V International | Tiempo Secure

Oct 11, 2022

RiVAI Technologies Announced New Products in Their RISC-V Vector DSP IP Family: RiVAI V7 And RiVAI V9+ | RiVAI Technologies

Oct 10, 2022

Make the Most of Rad-Hard RTG4 FPGAs with the Right Approach to Timing and Resets | Microchip Technology

Oct 6, 2022

RISC-V International Announces Agenda for RISC-V Summit 2022 | RISC-V International

Oct 3, 2022

Announcing RISC-V International’s Expanded Developer Boards Program | RISC-V International

Oct 3, 2022

DeepComputing and Xcalibyte announce the ROMA laptop will be powered by TH1520 – the first SoC from Wujian 600’s platform by Alibaba T-Head | Xcalibyte

Oct 2, 2022

XuanTie Security System Promotes Rapid Migration of Security Applications from Arm to RISC-V | Vincent Cui, Alibaba Cloud

Sep 27, 2022

Customising PolarFire® SoC FPGA for International Space Station Mission | Microchip Technology

Sep 12, 2022

Cortus Announces the Launch of its New Secure Low Power RISC-V Microcontrollers | Cortus S.A.S

Sep 7, 2022

Renodepedia – From Zephyr’s structured data to traceable and testable open hardware with Renode | Antmicro

Sep 5, 2022

SOC Verification Flows and Methodologies | Sivakumar P R, Maven Silicon

Aug 31, 2022

How will you share your RISC-V knowledge and wisdom? | RISC-V International

Aug 31, 2022

TRACE32® on XuanTie CPUs | LiFeng, Alibaba and Frank Xing, Lauterbach China

Aug 30, 2022

RISC-V International and Intel team up to accelerate RISC-V adoption: Introducing Intel Pathfinder for RISC-V | Intel Corporation

Aug 28, 2022

StarFive Announced 2 High-Performance RISC-V Products: JH7110 SoC and VisionFive 2 SBC | StarFive

Aug 25, 2022

Canonical enables Ubuntu on Allwinner’s Nezha RISC-V boards | Canonical

Aug 24, 2022

Versatile, Compact and High-Performance TySOM-M Embedded Development Board Based on PolarFire® SoC FPGA Device | Microchip Technologies

Aug 24, 2022

Alibaba Cloud Unveils Chip Development Platform to Support Developers with RISC-V based High-Performance SoCs | Alibaba Cloud

Aug 22, 2022

Canonical enables Ubuntu on StarFive’s VisionFive RISC-V boards | Ubuntu Blog, Canonical

Aug 21, 2022

T-Head DSA design in RISC-V | Chaojun Zhao, Alibaba Cloud

Aug 11, 2022

RISC-V Summit China 2022 Announces Agenda | RISC-V International

Aug 8, 2022

Defend Your Devices Against a Common and Insidious Hack With seL4 | Microchip Technologies

Aug 1, 2022

Welcoming RISC-V International Board Members

Jul 28, 2022

Architectures for Matrix Extension in CPU | Jiang Zhao, Alibaba Cloud

Jul 26, 2022

Porting GNOME OS to Microchip’s PolarFire® SoC FPGA Icicle Kit for the First Time | Microchip

Jul 18, 2022

Co-developing Machine Learning with a RISC-V vector core using Renode for Google Research | Antmicro

Jul 18, 2022

Accelerating ML Recommendation With Over 1,000 RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip | David R. Ditzel, Esperanto Technologies Inc

Jul 11, 2022

RISC-V Compressed Instructions for SERV | Abdul Wadood, LFX Mentorship at RISC-V International

Jul 11, 2022

Everything RISC-V at the Design Automation Conference! | RISC-V International

Jul 9, 2022

Progress in Porting Android onto RISC-V: Android 12 upgrade, vendor modules and TensorFlow Lite | Mao Han, Alibaba Cloud

Jul 7, 2022

PolarFire® SoC FPGA in Conclusive RCHD-PF System Module | Microchip

Jul 1, 2022

DeepComputing and Xcalibyte Open Pre-Orders for First Native RISC-V Development Laptop; Quantities Limited | Xcalibyte and Deep Computing

Jun 27, 2022

SoC Design Challenge: the first engineering hackathon for students in Russia | Nickolay Ternovoy, Syntacore

Jun 20, 2022

Democratizing Chiplet-Based Processor Design | Ventana Micro Systems

Jun 20, 2022

RISC-V Vector Processing is Taking Off | SiFive

Jun 20, 2022

GreenWaves will Demonstrate Live the Ground-breaking AI and DSP Demos on its Ultra Low Power Chip at Embedded World 2022 | GreenWaves Technologies

Jun 20, 2022

Overtake the Competition in Automotive Design with RISC-V Innovations | Codasip

Jun 17, 2022

Renode 1.13 for improved machine learning and pre-silicon development | Antmicro

Jun 16, 2022

Thermal (IR) Imaging Pipeline (ISP) Core on PolarFire® SoC FPGA SoM | Microchip

Jun 13, 2022

XuanTie C906 Tops MLPerf Tiny v0.7 Benchmark | MengChang, Alibaba Cloud

Jun 8, 2022

Why MIPS is Betting Big on RISC-V: Q&A with RISC-V International and MIPS | MIPS

Jun 2, 2022

RISC-V Summit China 2022 Call for Talks is Now Open

May 23, 2022

Simplifying the Vehicle to Anything (V2X) Journey: Porting of Jamaica VM on PolarFire® SoC Icicle Kit | Leah Iris, Microchip

May 10, 2022

MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability | MIPS

May 3, 2022

E4 Computer Engineering joins RISC-V International | E4 Computer Engineering

Apr 28, 2022

RISC-V Open Era of Computing – A Conversation with Calista Redmond and Mr. Sivakumar P R , Founder and CEO of Maven Silicon | Maven Silicon

Apr 25, 2022

Join us in the classroom! Put RISC-V into your Computer Architecture course using RVfpga! | Robert C.W. Owen, Imagination Technologies

Apr 20, 2022

Alibaba Cloud Tops MLPerf Tiny v0.7 Benchmark | Alibaba Cloud

Apr 19, 2022

Xuantie IOMMU from T-Head for RISC-V | Chong Ren, Alibaba Cloud

Apr 5, 2022

Mi-V Ecosystem Partner Solutions | Leah Iris, Microchip

Apr 4, 2022

XuanTie VirtualZone: RISC-V-based Security Extensions | Xuan Jian, Alibaba Cloud

Mar 15, 2022

RISC-V RV32I JALR Instruction | Maven Silicon

Feb 17, 2022

FOSSi Explosion 2021 | Olof Kindgren, FOSSi Foundation and Qamcom

Feb 7, 2022

Intel Corporation Makes Deep Investment in RISC-V Community to Accelerate Innovation in Open Computing

Feb 4, 2022

RISC-V RV32I J-Type | Maven Silicon

Feb 2, 2022

Semico Research’s New Report Predicts There Will Be 25 Billion RISC-V-Based AI SoCs By 2027 | Rich Wawrzyniak, Semico Research Corporation

Jan 31, 2022

Open source FPGA platform for Rowhammer security testing in the data center | Antmicro

Jan 27, 2022

Alibaba Cloud Opens Up IoT Technology Development Platform | Wang Cindy, Alibaba Cloud

Jan 12, 2022

RISC-V RV32I S-Type | Maven Silicon

Jan 4, 2022

Edge AI on Low-Footprint RISC-V | Alexander Stanitzki, Fraunhofer IMS

Dec 6, 2021

Next generation music AI engine available for RISC-V

Nov 18, 2021

See Western Digital’s SweRV Core family at the 2021 RISC-V Summit

Nov 5, 2021

How the Imagination RVfpga: Understanding Computer Architecture course is giving engineering under-grads real-world skills | Robert Owen, Imagination Technologies

Nov 3, 2021

Improving the OpenLane ASIC build flow with open source SystemVerilog support | Antmicro

Nov 2, 2021

How Alibaba is Porting RISC-V to the Android OS | Guoyin Chen, Alibaba

Oct 29, 2021

Automatic SystemVerilog linting in GitHub Actions with Verible | Antmicro

Oct 28, 2021

RISC-V RV32I I-Type | Maven Silicon

Oct 26, 2021

Recap of the Fall 2021 CHIPS Alliance Workshop | Rob Mains, CHIPS Alliance

Oct 19, 2021

De-RISC – The H2020 Project Which Will Create The First RISC-V Fully European Platform For Aerospace, Celebrates Its Second Anniversary | Ana Rísquez Navarro, De-RISC

Oct 13, 2021

ZAYA Now Offers Trusted Execution Environment For RISC-V | ZAYA

Oct 7, 2021

RISC-V Mentorship: Formal Verification of SweRV EL2 Processor | Shashank V.M.

Oct 5, 2021

How RISC-V and CHIPS Alliance are Driving a New Unified Memory Architecture Standard | CHIPS Alliance

Oct 1, 2021

Agenda for the RISC-V Summit 2021: Together We Are Shaping the Open Era of Computing

Sep 27, 2021

Privileged Specification Version 1.12 Now Open to Public Review

Sep 24, 2021

Developing standards-based verification environments for extensible RISC-V processor cores | Kevin McDermott, Imperas Software

Sep 22, 2021

…and out come SweRVolf | Olof Kindgren, Qamcom

Sep 9, 2021

LAST CHANCE TO SUBMIT YOUR TALK TO THE 2021 RISC-V SUMMIT!

Sep 3, 2021

RISC-V Cryptography Extensions Task Group Announces Public Review of the Scalar Cryptography Extensions

Aug 30, 2021

Google Summer of Code’21 at FOSSi Foundation: TensorCore Extension for Deep Learning | Nitin Mishra

Aug 26, 2021

Open source custom GitHub Actions runners with Google Cloud and Terraform | Antmicro

Aug 23, 2021

Google Summer of Code’21 at FOSSI Foundation: M-extension Support for SERV | Zeeshan Rafique, RISC-V Ambassador

Aug 17, 2021

RISC-V RV32I R-Type | Maven Silicon

Aug 10, 2021

Announcing public review for RISC-V standard extensions Zfinx, Zdinx, Zhinx, and Zhinxmin

Aug 5, 2021

StarFive open source single board hardware platform will be officially released by the end of Q3 2021

Aug 3, 2021

seL4 Integrity Enforcement Proved for RISC-V

Aug 3, 2021

“中国信芯” 再迈一步，万向区块链携生态伙伴举办RISC-V区块链行业工作组首次公开活动

Jul 20, 2021

Life in a Formal Verification Lane | Shivani Shah

Jul 19, 2021

What You Need to Know About Verilator Open Source Tooling | Rob Mains, CHIPS Alliance

Jul 14, 2021

A Free RISC-V CPU Core Builder – Democratizing CPUs | Steve Hoover, Redwood EDA

Jul 12, 2021

RISC-V RV32I Assembly – Multiplication | Maven Silicon

Jul 8, 2021

The Importance of Increasing Diversity in the Open Source Community

Jul 6, 2021

NeuralScale: Industry Leading General Purpose Programmable NPU Architecture based on RISC-V

Jun 30, 2021

A Process Independent Power Optimised Register File Architecture

Jun 29, 2021

Wanxiang Blockchain Organized the First Public Activity of RISC-V Blockchain SIG with Partners

Jun 25, 2021

RISC: Open Hardware

Jun 21, 2021

Embedded Programming and IoT – Memory Management Criticality!

Jun 9, 2021

RISC-V SIG-HPC Enabling RISC-V in HPC, Supercomputers to the Edge, and Emerging AI/ML/DL HPC Workloads

Jun 7, 2021

RISC-V RV32I RTL Architecture | Maven Silicon

Jun 4, 2021

The Zephyr Project Celebrates 5th Anniversary with new members and inaugural Zephyr Developer Summit on June 8-10

Jun 3, 2021

Antmicro Open Source Portal launched

May 28, 2021

New Open Source Contributor Model: RISC-V Development Partners

May 14, 2021

Coming June 2 – RISC-V Developer Tools and Tool Chains Forum! Register now!

May 13, 2021

RISC-V RV32I Instructions Format | Maven Silicon

May 5, 2021

seL4 on RISC-V Verified to Binary Code

May 3, 2021

The world’s first DSP based on RISC-V ISA is about to be mass-produced

Apr 28, 2021

RISC-V Developer Boards to drive innovation

Apr 19, 2021

Bugs: A verification engineer’s dream, a designer’s nightmare

Apr 8, 2021

RISC-V Application to Machine Language | Maven Silicon

Mar 31, 2021

Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT project

Mar 29, 2021

Opening Up New Design Possibilities with OmniXtend

Mar 25, 2021

The Cybersecurity Pincushion and a Myriad of Tiny Threat Points

Mar 22, 2021

Check out the new RISC-V Careers page and RISC-V Mentorship program!

Mar 19, 2021

FOSSi Fever 2020

Mar 17, 2021

RISC-V Security Forum 2021 – Schedule Announced!

Mar 9, 2021

Growing an Open and Inclusive Community

Mar 5, 2021

RISC-V Execution Stages | Maven Silicon

Mar 1, 2021

RISC-V Star Rising from the East – Introducing StarFive

Mar 1, 2021

RISC-V growth and successes in technology and industry : embedded world 2021

Feb 23, 2021

OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IP

Feb 12, 2021

RISC-V Becoming Less Risky with the Right Verification

Feb 11, 2021

High-throughput open source PCIe on Xilinx VU19P-based ASIC prototyping platform

Feb 5, 2021

Hardware Description Language Chisel & Diplomacy Deeper dive

Jan 29, 2021

Where to start with RISC-V

Jan 21, 2021

Overview of Diplomacy for writing effective hardware design language Chisel (Japanese)

Jan 20, 2021

RISC-V CPU Performance | Maven Silicon

Jan 6, 2021

Let’s Make RISC-V Connected Systems Synonymous with Security

Dec 15, 2020

RISC-V Microarchitecture for Kids??!! | Steve Hoover, Redwood EDA

Nov 29, 2020

What is Processor Core Complexity?

Nov 25, 2020

What is Needed to Support an Operating System?

Nov 23, 2020

Understanding the Performance of Processor IP Cores

Nov 18, 2020

RPC DRAM support in open source DRAM controller

Nov 13, 2020

13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core

Nov 12, 2020

PicoRio: the Raspberry Pi-like Small-Board Computer for RISC-V

Nov 10, 2020

Open Source Digital Library in HPC

Nov 9, 2020

PolarFire SoC and RISC-V

Nov 2, 2020

Third Workshop on RISC-V Activities – It’s the ecosystem!

Oct 29, 2020

RISC-V Global Forum 2020 Transparency Report

Oct 12, 2020

Move fast and break things? Not so fast in embedded.

Oct 2, 2020

Maven Silicon – a RISC-V Training Partner

Oct 1, 2020

RISC-V: Standing on the Shoulders of Giants

Sep 30, 2020

RISC-V: A Playground for Game-changing Design Methodologies

Sep 28, 2020

PicoRio for RISC-V like Raspberry Pi for ARM!

Sep 17, 2020

RISC-V Catalyst for Change

Sep 17, 2020

The Incredible Opportunity For SiFive | A note from SiFive President & CEO, Patrick Little

Sep 10, 2020

Building RISC-V systems on the secure seL4 microkernel in Renode – Antmicro

Sep 9, 2020

When 32 bits isn't enough — Porting Zephyr to RISCV64

Sep 8, 2020

RISC-V Global Forum – It's a wrap!

Sep 1, 2020

RISC-V Global Forum: Initiate. Innovate. Impact.

Aug 31, 2020

OpenHW open source CORE-V processor IP: a RISC-V story that leads with verification

Aug 26, 2020

Unlocking JavaScript: V8-RISCV Open Sourced

Aug 17, 2020

RISC-V Training Partners Bring professional learning to the worldwide community!

Aug 14, 2020

New RISC-V Director of Marketing: Increasing Visibility of the RISC-V Revolution

Aug 4, 2020

Welcoming RISC-V International Board Members

Jul 24, 2020

RISC-V Global Forum: Technology. Opportunity. Community.

Jul 8, 2020

Unleash Memory and Storage to Enable Next Generation Architectures

Jun 8, 2020

seL4 is verified on RISC-V!

Jun 8, 2020

seL4 operating system protects critical systems on RISC-V architecture from cyber-attacks

Jun 3, 2020

Strengthening the Internet of Things with a Secure RISC-V IoT Stack

Jun 1, 2020

Q&A with RISC-V Ambassador Wei Fu on the Growth and Future of RISC-V

May 21, 2020

Special Edition: Embedded World 2020 – Codasip

May 21, 2020

Special Edition: Embedded World 2020 – GreenWaves

May 19, 2020

Special Edition: Embedded World 2020 – Embecosm

May 19, 2020

Special Edition: Embedded World 2020 – Syntacore

May 19, 2020

Special Edition: Embedded World 2020 – CloudBear

May 18, 2020

Getting Started with RISC-V Verification

May 15, 2020

Special Edition: Embedded World 2020 – SiFive

May 15, 2020

Special Edition: Embedded World 2020 – Imperas

May 15, 2020

Special Edition: Embedded World 2020 – Andes Technologies

May 13, 2020

Trace Techniques for RISC-V – How to Use it Efficiently | Robert Chyla and Thomas Andersson, IAR Systems

May 4, 2020

Q&A with RISC-V Ambassador Florian Wohlrab on the Growth and Future of RISC-V

Apr 13, 2020

New Video: RISC-V Revolution

Apr 9, 2020

Celebration of IoT Day 2020: How Open Hardware & Software Is Stimulating IoT Innovation

Apr 8, 2020

RISC-V: An Open Source Approach Accelerating EDA Implementations

Apr 6, 2020

Special Edition: Embedded World 2020 – UltraSoC

Mar 31, 2020

Calista Redmond: Welcome to the RISC-V Revolution

Mar 30, 2020

The Importance of a Standardized Processor Trace

Mar 16, 2020

RISC-V: An Open Approach to System Security

Feb 28, 2020

HIPEAC 2020 Keynote 2: Calista Redmond on the RISC-V Revolution

Feb 28, 2020

RISC-V's Calista Redmond on the Open ISA Revolution | HiPEAC

Feb 18, 2020

RISC-V is not an "open-source processor" | Krste Asanovic, Chairman of the Board, RISC-V

Dec 20, 2019

Highlights from the 2019 RISC-V Summit: a Look at the Future of Computing

Dec 19, 2019

HotChips RISC-V Tutorial Video Now Available

Dec 3, 2019

Final Countdown to RISC-V Summit in San Jose

Sep 12, 2019

RISC-V EMEA Roadshow Spotlight: Imperas

Sep 12, 2019

RISC-V EMEA Roadshow Spotlight: AdaCore

Sep 10, 2019

Elektor article: A Microprocessor Made From Carbon Nanotube FETs

Sep 4, 2019

RISC-V EMEA Roadshow Spotlight: Andes Technology

Aug 28, 2019

RISC-V EMEA Roadshow Spotlight: Microchip Technology

Aug 21, 2019

RISC-V EMEA Roadshow Spotlight: OneSpin Solutions

Aug 14, 2019

RISC-V EMEA Roadshow Spotlight: GreenWaves Technologies

Aug 7, 2019

RISC-V EMEA Roadshow Spotlight: Western Digital

Jul 31, 2019

RISC-V EMEA Roadshow Spotlight: MINRES Technologies

Jul 25, 2019

RISC-V EMEA Roadshow Spotlight: Trinamic Motion Control

Apr 1, 2019

Key Priorities for Accelerating the RISC-V Revolution

Feb 19, 2019

RISC-V E-Newsletter Winter 2019

Dec 21, 2018

RISC-V ISA Motivates Youth

Dec 13, 2018

RISC-V SoftCPU Contest Highlights

Nov 29, 2018

Protected: RISC-V Summit Press Kit

Oct 8, 2018

RISC-V Design Contest Calls On Embedded Designers To Push The Limits Of Innovation

Sep 26, 2018

Recap Of The Third Bay Area RISC-V Meetup At Rambus

Jun 7, 2018

RISC-V E-Newsletter Summer 2018

Mar 20, 2018

A Look Back at the Evolution of RISC-V and a Peek at What’s Next from Krste Asanović

Feb 23, 2018

RISC-V E-Newsletter Winter 2018

Jan 4, 2018

Building a More Secure World with the RISC-V ISA

Oct 20, 2017

RISC-V E-Newsletter October 2017

Jun 30, 2017

RISC-V E-Newsletter June 2017

Apr 22, 2017

The RISC-V Memory Consistency Model

Mar 3, 2016

Charting a New Course for Semiconductors

Jul 1, 2015

Thanks to Everyone for a Successful 2nd RISC-V Workshop!

Jun 25, 2015

Open vs. Proprietary ISAs at CARD 2015

Jan 13, 2015

A Linux Distribution for RISC-V

Oct 12, 2014

Why Not Build on OpenRISC?

Oct 7, 2014

About our Dhrystone Benchmarking Methodology

Jul 29, 2014

RISC-V QEMU port

Jul 2, 2014

RISC-V GDB port

Mar 5, 2014

Boot RISC-V Linux in your web browser!

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Becoming a member of RISC-V International allows companies and individuals to actively influence the development of an open, royalty-free instruction set architecture, driving innovation in custom processor designs.