RISC-V Workshop in Chennai
July 18-19, 2018
The RISC-V Workshop in Chennai, India took place July 18-19, 2018. Hosted by The Indian Institute of Technology Madras (IIT Madras) and sponsored by Western Digital, the RISC-V Workshop in Chennai discussed current and prospective RISC-V projects and implementations to influence the future evolution of the instruction set architecture (ISA) from Silicon Valley to Silicon Fenn and beyond.
The event featured in-depth technical presentations and updates on the RISC-V architecture, a speaking lineup from leading technology companies and research institutions in the RISC-V ecosystem, opportunities for networking and a demo zone showing the latest innovations in the market.
Proceedings
Check out the slides from each of the sessions below.
Wednesday, July 18, 2018
| Time | Event | Speaker, Affiliation | Slides |
| 8:00 am | Registration & Breakfast | ||
| 8:55 am | Welcome address and about the Workshop | Kamakoti Veezinathan, IIT Madras and G S Madhusudan, InCore Semiconductors | |
| 9:00 am | RISC-V ISA & Foundation Overview | Rick O’Connor, RISC-V Foundation | Slides | Video |
| 9:15 am | RISCV ISA: Understanding Limitations and Methods to Improve Code Density & Performance | Gnanasekar Rajakumar and Ravikumar Gaddam, Western Digital | Slides | Video |
| 9:30 am | Going Beyond the RISC-V General Purpose Solutions | Neel Gala, InCore Semiconductors | Slides | Video |
| 10:00 am | Architecture Exploration of RISC-V Processor and Comparison with ARM Cortex A53 and A72 | Karthikeyan Sugumaran and Tom Jose, Mirabilis Design | Slides | Video |
| 10:30 am | Networking Break | ||
| 11:00 am | It’s Not About the Core, It’s About the System | Gajinder Panesar, UltraSoC | Slides | Video |
| 11:30 am | RiTA: RISC-V Trace Analyzer | Anmol Sahoo, IIT Madras and Neel Gala, InCore Semiconductors | Slides | Video |
| 11:45 am | KEYNOTE: RISC-V: Enabling a New Era of Open Data-Centric Computing Architectures | Vivek Tyagi, Western Digital | Slides | Video |
| 12:10 pm | Networking Lunch | ||
| 13:30 pm | Accelerating the RISC-V Revolution: Unleashing Custom Silicon with Revolutionary Design Platforms and Custom Accelerators | Huzefa Cutlerywala, SiFive | Slides | Video |
| 14:00 pm | Mi-V RISC-V Embedded Ecosystem | Krishnakumar Ranamoorthi, Microsemi | Slides | Video |
| 14:15 pm | Verification of the PULPino SoC Platform Using UVM | Mahesh R, Cisma Consultants and Shamanth HK, Cisma Consultants | Slides | Video |
| 14:30 pm | Porting Graphical Stacks to RISC-V using QEMU and Yocto | Atish Patra, Western Digital | Slides | Video |
| 14:45 pm | Networking Break | ||
| 15:15 pm | Panel: Evolving a RISC-V Based Ecosystem in India | Vivek Tyagi, Western Digital Konala Varma, Intel Mahesha Nanjundaiah, HPE Asutosh Upadhyay, Axilor Ventures Amudhan Balasubramanian, HCL Technologies G S Madhusudan, InCore Semiconductors |
Video |
| 16:15 pm | Poster / Demo Previews | Andrea Bocco and Tiago Trevian Jost, CEA LETI Shubhodeep Choudhury, Valtrix Kevin McDermott, Imperas Software Atish Patra, Western Digital Gajinder Panesar, UltraSoC |
Slides (CEA LETI) Slides (Valtrix) Slides (Imperas) Slides (Western Digital) Slides (UltraSoC) Video |
| 17:00 pm | Evening Reception, Poster Sessions and Demos |
Thursday, July 19, 2018
| Time | Event | Speaker, Affiliation | Slides |
| 8:00 am | Registration & Breakfast | ||
| 9:00 am | RISC-V Software Development Methodology for RISC-V Devices with RTOS and Linux or Both | Kevin McDermott, Imperas Software | Slides | Video |
| 9:30 am | Linux Kernel on RISC-V: Where Do We Stand? | Atish Patra and Damien Le Moal, Western Digital | Slides | Video |
| 10:00 am | A Comprehensive Framework For Power-Based Side-Channel Leakage Evaluation of SHAKTI C-Class | Muhammad Arsath and Chester Rebeiro, IIT Madras | Slides | Video |
| 10:30 am | Networking Break | ||
| 11:00 am | RISECREEK: From RISC-V Spec to 22FFL Silicon | Vinod Ganesan and Gopinathan Muthuswamy, IIT Madras | Slides | Video |
| 11:30 am | Shakti M-Class Libre RISC-V SoC | Luke Leighton, Independent | Slides | Video |
| 12:00 pm | SLSV: The Shakti LockStep Verification Framework | Paul George and Lavanya Jagan, IIT Madras | Slides | Video |
| 12:30 pm | Networking Lunch | ||
| 14:00 pm | A Survey of E31 RISC-V Core Floor-Plan and Its Impact on Power, Performance and Area (PPA) | Kunal Ghosh and Anagha Ghosh, VLSI System Design | Slides | Video |
| 14:30 pm | Integrating Gen-Z in Server-Class RISC-V Processors | Mohan Parthasarathy, HPE | Slides | Video |
| 15:00 | Formal Specification of the RISC-V Instruction Set Architecture | Rishiyur Nikhil and Niraj Sharma, Bluespec | Slides | Video |
| 15:30 pm | RISC-V Workshop Chennai Conclusion | Rick O’Connor, RISC-V Foundation | Video |