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The latest from RISC-V International and community members.

SUBMIT BLOG POST
Developing and testing heterogeneous space-grade systems with Renode

While landing humans on the Moon was a feat accomplished with very basic compute power of 2MHz provided by the Apollo Guidance Computer, modern spacecraft…

Whether you're a student aiming to complement your university education or a professional in the process of transitioning to RISC-V, check out our Top 3…

Announcing The Fourth International Workshop on RISC-V for HPC

The RISC-V HPC Special Interest Group is organising a workshop at ISC24, one of the leading High Performance Computing (HPC) conferences. The workshop will run…

Integrating ROS 2 With Microchip’s PolarFire® SoC FPGA

ROS (Robot Operating System) is a popular open-source framework used for creating robotics applications. It provides a set of tools and libraries for building complex…

OPC UA on PolarFire SoC: Enabling Industrial Edge Solutions

Webpage: https://www.microchip.com/en-us/solutions/industrial/fpga/opc-ua  Author: Apurva Peri, Principal Engineer, FPGA Product Marketing  The Modern Industrial Edge The Industrial Edge has become the standard for industrial automation requirements,…

The Rise of RISC-V – Analyzing Market Trends and Ecosystem Dynamics

Author- Rich Wawrzyniak Principal Analyst at The SHD Group As we start 2024, The SHD Group has released a comprehensive market analysis report titled "RISC-V…

Expanding RISC-V support in Renode with Bit-Manipulation extensions

Antmicro’s open source Renode simulation framework offers support for various instruction set architectures, with the RISC-V ISA being a major focus for – as a…

Five years of SERVing

Author: Olof Kindgren Making your own RISC-V CPU is a terrible idea. I have said that many times before. There are already a million RISC-V…

The Top 10 RISC-V Milestones & Highlights from 2023

Looking back at 2023, there are many different ways to measure progress and success. You could point to the growing adoption of RISC-V—which is in…

Developing and testing with Renode in heterogeneous, multi-node automotive use cases

Automotive engineering in the past 30 years has been transformed by the growing capabilities of microprocessors, enabling their use in a wide range of the…

Solving bus and software deadlock problems in complex SoCs

By: Siemens | Tessent Embedded Analytics | Author: Huw Geddes, Product Manager Intermittent bus and software deadlocks are amongst the toughest problems for development teams…

RISC-V Summit 2023: RISC-V is Here for Developers!

RISC-V Summit North America 2023 brought the RISC-V ecosystem together to share the latest technology solutions, proving that #riscvishere! A key takeaway from the show…

Developing and testing heterogeneous space-grade systems with Renode

While landing humans on the Moon was a feat accomplished with very basic compute power of 2MHz provided by the Apollo Guidance Computer, modern spacecraft…

Whether you're a student aiming to complement your university education or a professional in the process of transitioning to RISC-V, check out our Top 3…

Announcing The Fourth International Workshop on RISC-V for HPC

The RISC-V HPC Special Interest Group is organising a workshop at ISC24, one of the leading High Performance Computing (HPC) conferences. The workshop will run…

Integrating ROS 2 With Microchip’s PolarFire® SoC FPGA

ROS (Robot Operating System) is a popular open-source framework used for creating robotics applications. It provides a set of tools and libraries for building complex…

OPC UA on PolarFire SoC: Enabling Industrial Edge Solutions

Webpage: https://www.microchip.com/en-us/solutions/industrial/fpga/opc-ua  Author: Apurva Peri, Principal Engineer, FPGA Product Marketing  The Modern Industrial Edge The Industrial Edge has become the standard for industrial automation requirements,…

The Rise of RISC-V – Analyzing Market Trends and Ecosystem Dynamics

Author- Rich Wawrzyniak Principal Analyst at The SHD Group As we start 2024, The SHD Group has released a comprehensive market analysis report titled "RISC-V…

Expanding RISC-V support in Renode with Bit-Manipulation extensions

Antmicro’s open source Renode simulation framework offers support for various instruction set architectures, with the RISC-V ISA being a major focus for – as a…

Five years of SERVing

Author: Olof Kindgren Making your own RISC-V CPU is a terrible idea. I have said that many times before. There are already a million RISC-V…

The Top 10 RISC-V Milestones & Highlights from 2023

Looking back at 2023, there are many different ways to measure progress and success. You could point to the growing adoption of RISC-V—which is in…

Developing and testing with Renode in heterogeneous, multi-node automotive use cases

Automotive engineering in the past 30 years has been transformed by the growing capabilities of microprocessors, enabling their use in a wide range of the…

Solving bus and software deadlock problems in complex SoCs

By: Siemens | Tessent Embedded Analytics | Author: Huw Geddes, Product Manager Intermittent bus and software deadlocks are amongst the toughest problems for development teams…

RISC-V Summit 2023: RISC-V is Here for Developers!

RISC-V Summit North America 2023 brought the RISC-V ecosystem together to share the latest technology solutions, proving that #riscvishere! A key takeaway from the show…